ISL51002 Datasheet, PDF (6/32 Pages) Intersil Corporation – 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

Timing Diagrams
Data Output Setup and Hold Timing
DATACLK
ISL51002
DATACLK
PIXEL DATA
t_SETUP
t_HOLD
RGB Output Data Timing and Latency
HSYNC_IN
ANALOG
VIDEO IN
DATACLK
R/G/B[9:0]
HS_OUT
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED
TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST
OF THE AFE’S OUTPUT SIGNALS
P₀
P₁
P₂
P₃
P₄
P₅
P₆
P₇
P₈
P₉
P₁₀
P₁₁
P₁₂
8 DATACLK PIPELINE LATENCY
PROGRAMMABLE
WIDTH AND POLARITY
D₀
D₁
D₂
D₃
YUV Output Data Timing and Latency
HSYNCIN
ANALOG
VIDEO IN
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO.
THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE
AFE’S OUTPUT SIGNALS
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
DATACLK
G[9:0]
8 DATACLK PIPELINE LATENCY
G0 (YO) G1 (Y1) G2 (Y2) G3 (Y3)
R[9:0]
B0 (UO) R0 (V0) B2 (U2) R2 (V2)
B[9:0]
HSOUT
PROGRAMMABLE
WIDTH AND POLARITY
6
December 22, 2006