ISL51002 Datasheet, PDF (29/32 Pages) Intersil Corporation – 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

ISL51002
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 3), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 5). To achieve this, data being written to the
ISL51002 is latched on a delayed version of the rising edge
of SCL. SCL is delayed and deglitched inside the ISL51002
for three crystal clock periods (120ns for a 25MHz crystal) to
eliminate spurious clock pulses that could disrupt serial
communication.
When the contents of the ISL51002 are being read, the SDA
line is updated after the falling edge of SCL, delayed and
deglitched in the same manner.
Configuration Register Write
Figure 6 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 7 shows two views of the steps necessary to read one
or more words from the Configuration Register.
SCL
SDA
START
STOP
FIGURE 3. VALID START AND STOP CONDITIONS
SCL FROM
HOST
1
DATA OUTPUT
FROM TRANSMITTER
8
9
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER
SCL
SDA
DATA STABLE
DATA CHANGE DATA STABLE
FIGURE 5. VALID DATA CHANGES ON THE SDA BUS
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December 22, 2006