ISL51002 Datasheet, PDF (21/32 Pages) Intersil Corporation – 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

ISL51002
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
0x56
Transition threshold, (0x0A) 7:0 PADJ Threshold
0x57
0x58
0x59
0x5A
0x60
0x61
Phase Adjust Data 3, (read
only)
Phase Adjust Data 2, (read
only)
Phase Adjust Data 1, (read
only)
Phase Adjust Data 0, (read
only)
AFE CTRL, (0x00)
7:0 Reserved
7:0 Reserved
7:0 Reserved
7:0 Reserved
0 Reserved
1 700mV calibration
2 Coast Clamp Enable
3 Reserved
4 Blue Midscale
5 Green Midscale
6 Red Midscale
7 Midscale Override
ADC CTRL, (0x00)
0 Dither Enable
1 Dither Amplitude
3:2 Dither Increment
4 Dither Seed Reset
DESCRIPTION
Threshold of transitions visible for capturing. These are the 8
MSBs of the 10-bit threshold word used for phase quality
measurements. The actual 10-bit threshold used equals the
value in this register times 4.
Reserved
Reserved
Reserved
Reserved
Set to 0
0: Normal operation
1: All three inputs connected to internal ~700mV reference
voltage
0: DC restore clamping and ABLC suspended during Coast
and Macrovision (default)
1: DC restore clamping and ABLC continue during Coast
Set to 0
0: Half scale analog shift not added to Blue Channel (UV)
1: Half scale analog shift added to Blue Channel (YRGB)
0: Half scale analog shift not added to Green Channel (UV)
1: Half scale analog shift added to Green Channel (YRGB)
0: Half scale analog shift not added to Red Channel (UV)
1: Half scale analog shift added to Red Channel (YRGB)
0: Midscale determined by RGB/YUV bit in User Control
section – settings in 0x60[6:4] are ignored (default).
1: Midscale determined by 0x60[6:4]
0: Dither disabled (default)
1: Dither enabled
0: 16 LSBs (default)
1: 8 LSBs
00: Every Pixel (default)
01: Every HSYNC
10 and 11: Every VSYNC
Set to 1 and then to 0 to reset
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December 22, 2006