ISL51002 Datasheet, PDF (23/32 Pages) Intersil Corporation – 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

ISL51002
The offset controls shift the entire RGB input range, changing
the input image brightness. Three separate registers provide
independent control of the R, G, and B channels. Their
nominal setting is 0x8000, which forces the ADC to output
code 0x0000 (or 0x200 for the R (Pr) and B (Pb) channels in
YPbPr mode) during the back porch period when ABLC™ is
enabled.
Functional Description
Inputs
The ISL51002 digitizes analog video inputs in both RGB
and Component (YPbPr) formats, with or without
embedded sync (SOG).
RGB Inputs
For RGB inputs, the black/blank levels are identical and equal
to 0V. The range for each color is typically 0V to 0.7V from
black to white. HSYNC and VSYNC are separate signals.
Component YPbPr Inputs
In addition to RGB and RGB with SOG, the ISL51002 has an
option that is compatible with the component YPbPr video
inputs typically generated by DVD players. While the
ISL51002 digitizes signals in these color spaces, it does not
perform color space conversion; if it digitizes an RGB signal,
it outputs digital RGB, while if it digitizes a YPbPr signal, it
outputs digital YCbCr, also called YUV.
The Luminance (Y) signal is applied to the Green Channel
and is processed in a manner identical to the Green input
with SOG described previously. The color difference signals
Pb and Pr are bipolar and swing both above and below the
black level. When the YPbPr mode is enabled, the black
level output for the color difference channels shifts to a mid
scale value of 0x200. Setting configuration register
0x10[4] = 1 enables the YPbPr signal processing mode of
operation.
TABLE 1. YUV MAPPING (4:4:4)
INPUT
SIGNAL
ISL51002
INPUT
CHANNEL
ISL51002
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y
Green
Green
Y₀Y₁Y₂Y₃
Pb
Blue
Blue
U₀U₁U₂U₃
Pr
Red
Red
V₀V₁V₂V₃
The ISL51002 can optionally decimate the incoming data to
provide a 4:2:2 output stream (configuration register
0x28[0] = 1) as shown in Table 2.
TABLE 2. YUV MAPPING (4:2:2)
INPUT
SIGNAL
ISL51002
INPUT
CHANNEL
ISL51002
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y
Green
Green
Y₀Y₁Y₂Y₃
Pb
Blue
Blue
Driven Low
Pr
Red
Red
U₀V₀U₂V₂
Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled
(See register 0x10[3]). AC coupling is usually preferred since
it allows video signals with substantial DC offsets to be
accurately digitized. The ISL51002 provides a complete
internal DC-restore function, including the DC restore clamp
(See Figure 1) and programmable clamp timing (registers
0x24, 0x25, and 0x26).
When AC-coupled, the DC restore clamp is applied every
line, a programmable number of pixels after the trailing edge
of HSYNC. If register 0x60[2] = 0 (the default), the clamp will
not be applied while the DPLL is coasting, preventing any
clamp voltage errors from composite sync edges,
equalization pulses, or Macrovision signals.
After the trailing edge of HSYNC, the DC restore clamp is
turned on after the number of pixels specified in the DC
Restore and ABLC™ Starting Pixel registers (0x24 and
0x25) has been reached. The clamp is applied for the
number of pixels specified by the DC Restore Clamp Width
Register (0x26). The clamp can be applied to the back porch
of the video, or to the front porch (by increasing the DC
Restore and ABLC™ Starting Pixel registers so all the active
video pixels are skipped).
Note: The TriLevel detect for Sync on Green (SOG) utilizes
the digitized data from the selected Green video channel. If
TriLevel Sync is present, the default DC Clamp start position
will clamp at the top of the TriLevel Sync pulse giving a false
negative for TriLevel detect and clamping off the bottom half
of the green video. If you have an indication of active SOG
you must move the clamp start to a value greater than 0x30
to check to see if the Tri-level Sync is present.
If DC-coupled operation is desired, the input to the ADC will
be the difference between the input signal (R_IN1, for
example) and that channel’s ground reference (RGB_GND1 in
that example).
23
December 22, 2006