ISL51002 Datasheet, PDF (12/32 Pages) Intersil Corporation – 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

ISL51002
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
0x04
Interrupt Status,
BITS
FUNCTION NAME
0 CH0 Sync Changed
Write a 1 to each bit to clear
it, 0xFF to clear all.
1 CH1 Sync Changed
2 CH2 Sync Changed
3 CH3 Sync Changed
4 Selected Input Channel
Disrupted
5 Selected Input Channel
Changed
0x05
Interrupt Mask Register,
(0xFF)
6 VSYNC INT
7 PADJ INT
0 CH0 Mask
1 CH1 Mask
2 CH2 Mask
3 CH3 Mask
4 Input Disrupted Mask
5 Input Changed Mask
6 VSYNC INT Mask
7 PADJ INT Mask
DESCRIPTION
0: No change
1: CH0 activity or polarity changed
0: No change
1: CH1 activity or polarity changed
0: No change
1: CH2 activity or polarity changed
0: No change
1: CH3 activity or polarity changed
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
signal has changed (fast notification of a mode change)
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
period or pulse width has settled to a new value and can be
measured
0: Default state
1: VSYNC occurred
0: Default state
1: Phase Adjustment function completed.
0: Generate interrupt if CH0 sync activity, polarity, period, or
pulse width changes
1: Mask CH0 interrupt
0: Generate interrupt if CH1 sync activity, polarity, period, or
pulse width changes
1: Mask CH1 interrupt
0: Generate interrupt if CH2 sync activity, polarity, period, or
pulse width changes
1: Mask CH2 interrupt
0: Generate interrupt if CH3 sync activity, polarity, period, or
pulse width changes
1: Mask CH3 interrupt
0: Generate interrupt if selected Input Channel’s sync inputs
are disrupted
1: Mask Input Channel interrupt
0: Generate interrupt after selected Input Channel period or
pulse width settles to new value
1: Mask Input Channel interrupt
0: Generate interrupt every VSYNC
1: Mask VSYNC Interrupt
0: Generate interrupt upon phase adjustment block request
completion
1: Mask Phase adjustment interrupt
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December 22, 2006