ISL12028_10 Datasheet, PDF (6/29 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12028, ISL12028A
Serial Interface (I²C) Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
MAX
TYP (Note 16) UNITS NOTES
t_AA
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of V_DD,
Data Valid
until SDA exits the 30% to 70% of V_DD
window.
900
ns
t_BUF Time the bus must be free before SDA crossing 70% of V_DD during a
1300
ns
the start of a new transmission
STOP condition, to SDA crossing 70%
of V_DD during the following START
condition.
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_HD:STO
t_DH
Cb
Clock LOW Time
Measured at the 30% of V_DD crossing.
Clock HIGH Time
Measured at the 70% of V_DD crossing.
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of V_DD.
START Condition Hold Time
From SDA falling edge crossing 30%
of V_DD to SCL falling edge crossing
70% of V_DD.
Input Data Setup Time
From SDA exiting the 30% to 70% of
V_DD window, to SCL rising edge
crossing 30% of V_DD
Input Data Hold Time
From SCL falling edge crossing 70%
of V_DD to SDA entering the 30% to
70% of V_DD window.
STOP Condition Setup Time
From SCL rising edge crossing 70% of
V_DD, to SDA rising edge crossing 30%
of V_DD.
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling
edge. Both crossing 70% of V_DD.
Output Data Hold Time
From SCL falling edge crossing 30%
of V_DD, until SDA enters the 30% to
70% of V_DD window.
Capacitive Loading of SDA or SCL Total on-chip and off-chip
1300
600
600
600
100
0
600
600
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
400
pF
Cpin SDA, and SCL Pin Capacitance
10
pF
t_WC Non-volatile Write Cycle Time
t_R
SDA and SCL Rise Time
From 30% to 70% of V_DD
t_F
SDA and SCL Fall Time
From 70% to 30% of V_DD
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
12
20
20 + 0.1 x Cb
250
20 + 0.1 x Cb
250
10
400
ms
14
ns
15
ns
15
pF
15
R_PU SDA and SCL Bus Pull-up Resistor Maximum is determined by t_R and t_F.
1
Off-chip
For Cb = 400pF, max is about
2kΩ~2.5kΩ.
For Cb = 40pF, max is about
15kΩ~20kΩ
kΩ
15
NOTES:
7. IRQ/F_OUT Inactive (no frequency output and no alarms).
8. V_IL = V_DD x 0.1, V_IH = V_DD x 0.9, f_SCL = 400kHz.
9. V_RESET = 2.63V (V_DD must be greater than V_RESET), V_BAT = 0V.
10. Bit BSW = 0 (Standard Mode), ATR = 00h, V_BAT ≥ 1.8V.
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the V_{DD SR-} specification must be followed.
13. Parameter is not 100% tested.
14. t_WC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I²C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
6
FN8233.8
August 9, 2010