ISL12028_10 Datasheet, PDF (17/29 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12028, ISL12028A
V_DD > V_BAT +V_BATHYS
The Legacy Mode power control conditions are illustrated in
Figure 15.
V_BAT
V_DD
OFF
VOLTAGE
ON
IN
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
Power On Reset
Application of power to the ISL12028 activates a Power On
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
- It prevents the processor from operating prior to
stabilization of the oscillator.
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
- It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When V_DD exceeds the device V_RESET threshold value for
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
NOTE: If the V_BAT voltage drops below the data sheet
minimum of 1.8V and the V_DD power cycles to 0V then back
to V_DD voltage, then the RESET output may stay low and the
I²C communications will not operate. The V_BAT and V_DD
power will need to be cycled to 0V together to allow normal
operation again.
Watchdog Timer Operation
The watchdog timer time-out period is selectable. By writing
a value to WD1 and WD0, the Watchdog timer can be set
to 3 different time-out periods or off. When the Watchdog
timer is set to off, the Watchdog circuit is configured for low
power operation. See Table 8.
TABLE 8. WATCHDOG TIMER OPERATION
WD1
WD0
DURATION
1
1
disabled
1
0
250ms
0
1
750ms
0
0
1.75s
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the Watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the Watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh Watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode (see Figure 3).
In battery mode, the Watchdog timer function is disabled.
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the V_DD line versus a preset threshold
voltage (V_RESET), then generates a RESET pulse if it is
below V_RESET. The reset pulse will time-out 250ms after the
V_DD line rises above V_RESET. If the V_DD remains below
V_RESET, then the RESET output will remain asserted low.
Power-up and power-down waveforms are shown in
Figure 4 on page 7. The LVR circuit is to be designed so the
RESET signal is valid down to V_DD = 1.0V.
When the LVR signal is active, unless the part has been
switched into the battery mode, the completion of an
in-progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
operations. See “I²C Communications During Battery
Backup and LVR Operation” on page 25.
In battery mode, the RESET signal output is asserted LOW
when the V_DD voltage supply has dipped below the V_RESET
threshold. The RESET signal output will not return HIGH
until the device is back to V_DD mode even the V_DD voltage is
above V_RESET threshold.
Serial Communication
The device supports the I²C bidirectional serial bus protocol.
CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 16).
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 17).
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
17
FN8233.8
August 9, 2010