ISL12028_10 Datasheet, PDF (12/29 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12028, ISL12028A
TABLE 2. CLOCK/CONTROL MEMORY MAP
BIT
REG
RANG
ADDR. TYPE NAME 7
6
5
4
3
2
1
0
E
003F
0037
0036
0035
0034
0033
0032
0031
0030
0014
0013
0012
0011
0010
Status
RTC
(SRAM)
Control
(EEPROM
)
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
PWR
DTR
ATR
INT
BL
BAT
0
0
Y23
0
0
MIL
0
0
SBIB
0
0
IM
BP2
AL1
0
0
Y22
0
0
0
M22
S22
BSW
0
0
AL1E
BP1
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
0
ATR5
AL0E
BP0
OSCF
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
0
ATR4
FO1
WD1
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
0
ATR3
FO0
WD0
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
VTS2
DTR2
ATR2
0
0
WEL
0
DY1
Y11
G11
D11
H11
M11
S11
VTS1
DTR1
ATR1
0
0
RTCF
01h 01h
Y2K10 19/20 20h 20h
DY0 0 to 6 00h 00h
Y10 0 to 99 00h 00h
G10 1 to 12 00h 00h
D10 1 to 31 01h 01h
H10 0 to 23 00h 00h
M10 0 to 59 00h 00h
S10 0 to 59 00h 00h
VTS0
4Xh 0Xh
DTR0
00h 00h
ATR0
00h 00h
0
00h 00h
0
18h 18h
000F Alarm1 Y2K1
0
0 A1Y2K21 A1Y2K20 A1Y2K13
0
0
A1Y2K10 19/20 20h 20h
000E ^(EEPROM DWA1 EDW1
0
0
0
0
DY2
DY1
DY0 0 to 6 00h 00h
)
000D
YRA1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
000C
MOA1 EMO1
0
0
A1G20 A1G13 A1G12 A1G11 A1G10 1 to 12 00h 00h
000B
DTA1 EDT1
0
A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1 to 31 00h 00h
000A
HRA1 EHR1
0
A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0 to 23 00h 00h
0009
MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0 to 59 00h 00h
0008
SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0 to 59 00h 00h
0007 Alarm0 Y2K0
0
0 A0Y2K21 A0Y2K20 A0Y2K13
0
0
A0Y2K10 19/20 20h 20h
0006 ^(EEPROM DWA0 EDW0
0
0
0
0
DY2
DY1
DY0 0 to 6 00h 00h
)
0005
YRA0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0004
MOA0 EMO0
0
0
A0G20 A0G13 A0G12 A0G11 A0G10 1 to 12 00h 00h
0003
DTA0 EDT0
0
A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1 to 31 00h 00h
0002
HRA0 EHR0
0
A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0 to 23 00h 00h
0001
MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0 to 59 00h 00h
0000
SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0 to 59 00h 00h
NOTE: Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation, see device
“Ordering Information on page 2).
Unused Bits
Bit 3 in the SR is not used, but must be zero. The Data Byte
output during a SR read will contain a zero in this bit
location.
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 14
and “Application Section” on page 22 for more information.
12
FN8233.8
August 9, 2010