ISL12028_10 Datasheet, PDF (14/29 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12028, ISL12028A
The effective series load capacitance is the combination of
C_X1 and C_X2 as shown in Equation 2:
CLOAD
=
----------------¹------------------
⎛
⎝
-----¹-----
C_X1
+
C^-----1_X^----₂^{-⎠⎞}
(EQ. 2)
CLOAD
=
⎛
⎝
1_---6_-----⋅_---b_---5_----+_-----8_----⋅_---b_---4_-----+_----4_----⋅_---b_----3_----+_----2_-2----⋅_---b_---2_----+_----1_-----⋅_---b_---1_----+_-----0_---._-5_----⋅_----b_---0_----+_----9_{--⎠⎞}
p
F
For example, C_LOAD(ATR = 00000) = 12.5pF, C_LOAD
(ATR = 100000) = 4.5pF, and C_LOAD(ATR = 011111) = 20.25pF.
The entire range for the series combination of load capacitance
goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these
are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using the three DTR bits.
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR REGISTER
DTR2
DTR1
DTR0
ESTIMATED FREQUENCY
PPM
0
0
0
0
0
1
0
+10
0
0
1
+20
0
1
1
+30
1
0
0
0
1
1
0
-10
1
0
1
-20
1
1
1
-30
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: - Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0”. (default is “0”). See
“RESET” on page 9 and “Power Control Operation” on
page 15.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V_DD and Back Up Battery. There are two
options.
Option 1 Standard Mode: Set “BSW = 0” (default for
ISL12028A)
Option 2 Legacy/Default Mode: Set “BSW = 1” (default for
ISL12028)
See “Power Control Operation” on page 15 for more details.
Also see “I²C Communications During Battery backup and
LVR Operation” in the “Application Section” on page 22 for
important details.
VTS2, VTS1, VTS0: V_RESET Select Bits
The ISL12028 is shipped with a default V_DD threshold
(V_RESET) per the “Ordering Information” table on page 2.
This register is a non-volatile with no protection, therefore
any writes to this location can change the default value from
that marked on the package. If not changed with a
non-volatile write, this value will not change over normal
operating and storage conditions. However, ISL12028 has
four (4) additional selectable levels to fit the customers
application. Levels are: 4.64V(default), 4.38V, 3.09V, 2.92V
and 2.63V. The V_RESET selection is via 3 bits (VTS2, VTS1
and VTS0) (see Table 6).
Care should be taken when changing the V_RESET select bits.
If the V_RESET voltage selected is higher than V_DD, then the
device will go into RESET and unless V_DD is increased, the
device will no longer be able to communicate using the I²C.
VTS2
0
0
0
0
1
TABLE 6. V_RESET SELECTION
VTS1
0
VTS0
0
V_RESET (V)
4.64
0
1
4.38
1
0
3.09
1
1
2.92
0
0
2.63
In battery mode, the RESET signal output is asserted LOW
when the V_DD voltage supply has dipped below the V_RESET
threshold, but the RESET signal output will not return HIGH
until the device is back to V_DD mode even the V_DD voltage is
above V_RESET threshold.
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers
requires the following steps:
1. Write a 02h to the Status Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
2. Write a 06h to the Status Register to set both the Register
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
14
FN8233.8
August 9, 2010