ISL12026_08 Datasheet, PDF (6/24 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

Write Cycle Timing
ISL12026, ISL12026A
SCL
SDA
8TH BIT OF LAST BYTE
ACK
t_WC
STOP
CONDITION
START
CONDITION
Typical Performance Curves Temperature is +25°C unless otherwise specified.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.8
BSW = 0 OR 1
SCL, SDA PULL-UPS = 0V
SCL, SDA PULL-UPS = V_BAT
BSW = 0 OR 1
2.3 2.8 3.3 3.8 4.3 4.8 5.3
V_BAT (V)
FIGURE 1. I_BAT vs V_BAT, SBIB = 0
0.9
0.8
0.7
SCL, SDA PULL-UPS = 0V
0.6
BSW = 0 OR 1
0.5
0.4
0.3
0.2
0.1
0.0
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V_BAT (V)
FIGURE 2. I_BAT vs V_BAT, SBIB = 1
5.0
4.5
4.0
V_DD = 5.5V
3.5
3.0
V_DD = 3.3V
2.5
2.0
1.5
1.0
0.5
0.0
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85
TEMPERATURE (°C)
FIGURE 3. I_DD3 vs TEMPERATURE
1.4
1.2
V_BAT = 3.0V
1.0
0.8
0.6
0.4
0.2
0.0
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85
TEMPERATURE (°C)
FIGURE 4. I_BAT vs TEMPERATURE
6
FN8231.8
October 28, 2008