ISL12026_08 Datasheet, PDF(12/24 Page) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

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ISL12026_08 Datasheet, PDF (12/24 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

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ISL12026, ISL12026A

DTR Register - DTR2, DTR1, DTR0: Digital

Trimming Register

The digital trimming Bits DTR2, DTR1 and DTR0 adjust the

number of counts per second and average the ppm error to

achieve better accuracy.

DTR2 is a sign bit. DTR2 = 0 means frequency

compensation is > 0. DTR2 = 1 means frequency

compensation is < 0.

DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm

adjustment and DTR0 gives 20 ppm adjustment.

A range from -30ppm to +30ppm can be represented by

using the three DTR bits.

TABLE 5. DIGITAL TRIMMING REGISTERS

DTR REGISTER

DTR2

DTR1

DTR0

ESTIMATED FREQUENCY

PPM

+10

+20

+30

-10

-20

-30

PWR Register: SBIB, BSW

SBIB: - Serial Bus Interface (Enable)

The serial bus can be disabled in battery backup mode by

setting this bit to â1â. This will minimize power drain on the

battery. The Serial Interface can be enabled in battery

backup mode by setting this bit to â0â. (default is â0â). See

âBSW: Power Control Bitâ on page 12.

BSW: Power Control Bit

The Power Control bit, BSW, determines the conditions for

switching between VDD and Backup Battery. There are two

options.

Option 1. Standard Mode: Set âBSW = 0â

Option 2. Legacy Mode: Set âBSW = 1â

See âPower Control Operationâ on page 13 for more details.

Also see âI2C Communications During Battery Backupâ on

page 22 for important details.

TABLE 6. VBAT TRIP POINT WITH DIFFERENT BSW SETTING

VBAT TRIP POINT

BSW BIT

(V)

POWER CONTROL SETTING

2.2

Standard Mode (ISL12026A)

VDD < VBAT

Legacy Mode (ISL12026)

Device Operation

Writing to the Clock/Control Registers

Changing any of the bits of the clock/control registers

requires the following steps:

1. Write a 02h to the Status Register to set the Write Enable

Latch (WEL). This is a volatile operation, so there is no

delay after the write (operation preceded by a start and

ended with a stop).

2. Write a 06h to the Status Register to set both the Register

Write Enable Latch (RWEL) and the WEL bit. This is also

a volatile cycle. The zeros in the data byte are required

(operation proceeded by a start and ended with a stop).

Write all 8 bytes to the RTC registers, or one byte to the SR,

or one to five bytes to the control registers. This sequence

starts with a start bit, requires a slave byte of â11011110â and

an address within the CCR and is terminated by a stop bit. A

write to the EEPROM registers in the CCR will initiate a non-

volatile write cycle and will take up to 20ms to complete. A

write to the RTC registers (SRAM) will require much shorter

cycle time (t = tBUF). Writes to undefined areas have no

effect. The RWEL bit is reset by the completion of a write to

the CCR, so the sequence must be repeated to again initiate

another change to the CCR contents. If the sequence is not

completed for any reason (by sending an incorrect number

of bits or sending a start instead of a stop, for example), the

RWEL bit is not reset and the device remains in an active

mode. Writing all zeros to the status register resets both the

WEL and RWEL bits. A read operation occurring between

any of the previous operations will not interrupt the register

write operation.

Alarm Operation

Since the alarm works as a comparison between the alarm

registers and the RTC registers, it is ideal for notifying a host

processor of a particular time event, which triggers some

action as a result. The host can be notified by either a

hardware interrupt (the IRQ/FOUT pin) or by polling the

Status Register (SR) Alarm bits. These two volatile bits

(AL1for Alarm 1 and AL0 for Alarm 0), indicate if an alarm

has happened. The bits are set on an alarm condition

regardless of whether the

IRQ/FOUT interrupt is enabled. The AL1 and AL0 bits in the

status register are reset by the falling edge of the eighth

clock of status register read.

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

1. Single Event Mode is enabled by setting the AL0E or

AL1E bit to â1â, the IM bit to â0â, and disabling the

frequency output. This mode permits a one-time match

between the alarm registers and the RTC registers. Once

this match occurs, the AL0 or AL1 bit is set to â1â and the

IRQ/FOUT output will be pulled low and will remain low

until the AL0 or AL1 bit is read, which will automatically

resets it. Both Alarm registers can be set at the same time

FN8231.8

October 28, 2008

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