ISL12026_08 Datasheet, PDF (4/24 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12026, ISL12026A
EEPROM Specifications
PARAMETER
EEPROM Endurance
EEPROM Retention
TEST CONDITIONS
Temperature ≤ +75°C
MIN
(Note 12)
TYP
>2,000,000
50
MAX
(Note 12)
UNITS
Cycles
Years
NOTES
Serial Interface (I²C) Specifications
DC Electrical Specifications
SYMBOL
PARAMETER
V_IL
SDA and SCL Input Buffer LOW
Voltage
V_IH
SDA and SCL Input Buffer HIGH
Voltage
Hysteresis SDA and SCL Input Buffer
Hysteresis
V_OL SDA Output Buffer LOW Voltage
I_LI
Input Leakage Current on SCL
I_LO
I/O Leakage Current on SDA
TEST CONDITIONS
I_OL = 4mA
V_IN = 5.5V
V_IN = 5.5V
MIN
(Note 12)
-0.3
TYP
MAX
(Note 12)
0.3xV_DD
UNITS
V
NOTES
0.7 x V_DD
V_DD + 0.3
V
0.05 x V_DD
V
13
0
0.4
V
100
nA
100
nA
AC Electrical Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
f_SCL SCL Frequency
t_IN
Pulse width Suppression Time at Any pulse narrower than the max
SDA and SCL Inputs
spec is suppressed.
t_AA
t_BUF
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
V_DD, until SDA exits the 30% to 70%
of V_DD window.
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of V_DD during a
STOP condition, to SDA crossing
70% of V_DD during the following
START condition.
t_LOW Clock LOW Time
Measured at the 30% of V_DD
crossing.
t_HIGH Clock HIGH Time
Measured at the 70% of V_DD
crossing.
t_SU:STA START Condition Set-up Time
t_HD:STA START Condition Hold Time
t_SU:DAT Input Data Set-up Time
t_HD:DAT Input Data Hold Time
SCL rising edge to SDA falling edge.
Both crossing 70% of V_DD.
From SDA falling edge crossing
30% of V_DD to SCL falling edge
crossing 70% of V_DD.
From SDA exiting the 30% to 70% of
V_DD window, to SCL rising edge
crossing 30% of V_DD.
From SCL rising edge crossing 70%
of V_DD to SDA entering the 30% to
70% of V_DD window.
MIN
(Note 12)
1300
1300
600
600
600
100
0
MAX
TYP (Note 12) UNITS NOTES
400
kHz
50
ns
900
ns
ns
ns
ns
ns
ns
ns
ns
4
FN8231.8
October 28, 2008