ISL12026_08 Datasheet, PDF (11/24 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12026, ISL12026A
TABLE 3.
PROTECTED ADDRESSES
ISL12026
ARRAY LOCK
000
None (Default)
None
001
010
011
100
101
110
111
180_h – 1FF_h
100_h – 1FF_h
000_h – 1FF_h
000_h – 03F_h
000_h – 07F_h
000_h – 0FF_h
000_h – 1FF_h
Upper 1/4
Upper 1/2
Full Array
First 4 Pages
First 8 Pages
First 16 Pages
Full Array
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output
(IRQ/F_OUT). The interrupts are enabled when either the
AL1E or AL0E or both bits are set to ‘1’ and both the FO1
and FO0 bits are set to 0 (F_OUT disabled).
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/F_OUT output will now be pulsed each time an
alarm occurs. This means that once the interrupt mode alarm
is set, it will continue to alarm for each occurring match of the
alarm and present time. This mode is convenient for hourly or
daily hardware interrupts in microcontroller applications such
as security cameras or utility meter reading.
In the case that both Alarm 0 and Alarm 1 are enabled, the
IRQ/F_OUT pin will be pulsed each time either alarm matches
the RTC (both alarms can provide hardware interrupt). If the
IM bit is also set to "1", the IRQ/F_OUT will be pulsed for each
of the alarms as well.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the
IRQ/F_OUT output pin. Table 4 shows the selection bits for
this output. When using this function, the Alarm output
function is disabled.
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
FO1 FO0
OUTPUT FREQUENCY
0
0
0
1
1
0
1
1
Alarm output (F_OUT disabled)
32.768kHz
4096Hz
1Hz
Oscillator Compensation Registers
There are two trimming options.
• ATR. Analog Trimming Register
• DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64 to +110 ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
6 analog trimming bits, ATR0 to ATR5, are provided in order
to adjust the on-chip load capacitance value for frequency
compensation of the RTC. Each bit has a different weight for
capacitance adjustment. For example, using a Citizen CFS-
206 crystal with different ATR bit combinations provides an
estimated ppm adjustment range from -34 to +80ppm to the
nominal frequency compensation.
X1
C_X1
X2
C_X2
CRYSTAL
OSCILLATOR
FIGURE 8. DIAGRAM OF ATR
The effective on-chip series load capacitance, C_LOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C_LOAD is changed via two digitally
controlled capacitors, C_X1 and C_X2, connected from the X1
and X2 pins to ground (see Figure 8). The value of C_X1 and
C_X2 is given by Equation 1:
CX = (16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9)pF
(EQ. 1)
The effective series load capacitance is the combination of
C_X1 and C_X2:
CLOAD
=
----------------¹------------------
⎛
⎝
-----¹-----
C_X1
+
C^-----1_X^----₂^{-⎠⎞}
CLOAD
=
⎛
⎝
-¹--⁶-----^â‹---^b---⁵----⁺-----⁸----^â‹---^b---⁴-----⁺----⁴----^â‹---^b----³----⁺----²-₂----^â‹---^b---²----⁺----¹-----^â‹---^b---¹----⁺-----⁰---^.-⁵----^â‹----^b---⁰----⁺----⁹--_⎠⎞
p
F
(EQ. 2)
For example, C_LOAD(ATR = 00000) = 12.5pF, C_LOAD
(ATR = 100000) = 4.5pF, and C_LOAD(ATR = 011111) = 20.25pF.
The entire range for the series combination of load capacitance
goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these
are typical values.
11
FN8231.8
October 28, 2008