82C50A_06 Datasheet, PDF (6/25 Pages) Intersil Corporation – CMOS Asynchronous

Block Diagram
(1 - 8)
D7 - D0
DATA BUS
BUFFER
(40)
+5V
POWER
GND
(20)
SUPPLY
(28)
A0
(27)
A1
(26)
A2
CS0
CS1
CS2
ADS
MR
DISTR
DISTR
DOSTR
DOSTR
DDIS
CSOUT
XTAL1
XTAL2
(12)
(13)
SELECT
&
(14)
CONTROL
(25)
LOGIC
(35)
(22)
(21)
(19)
(18)
(23)
(24)
(16)
(17)
SCRATCH
REGISTER
6
82C50A
RECEIVER BUFFER
REGISTER
LINE CONTROL
REGISTER
(10)
RECEIVER SHIFT
SIN
RECEIVER
(9)
RECEIVER TIMING
& CONTROL
RCLK
DIVISOR
LATCH (LS)
DIVISOR
LATCH (MS)
BAUD RATE
GENERATOR
(15)
BAUDOUT
LINE STATUS
REGISTER
TRANSMITTER
HOLDING REGISTER
MODEM CONTROL
REGISTER
MODEM STATUS
REGISTER
INTERRUPT ENABLE
REGISTER
INTERRUPT IO
REGISTER
TRANSMITTER
TIMING & CONTROL
TRANSMITTER (11)
SHIFT REGISTER
SOUT
MODEM
CONTROL
LOGIC
(32)
RTS
(33)
DTR
(34)
OUT1
(31)
OUT2
(36)
CTS
(37)
DSR
(38)
DCD
(39)
RI
INTERRUPT
CONTROL
LOGIC
(30)
INTRPT
FN2958.5
August 24, 2006