82C50A_06 Datasheet, PDF (13/25 Pages) Intersil Corporation – CMOS Asynchronous

82C50A
INTERRUPT ENABLE REGISTER (IER)
The Interrupt Enable Register (IER) is a Write register used
to independently enable the four 82C50A interrupts which
activate the interrupt (lNTRPT) output. All interrupts are
disabled by resetting IER(0) - IER(3) of the Interrupt Enable
Register. Interrupts are enabled by setting the appropriate
bits of the IER high. Disabling the interrupt system inhibits
the Interrupt Identification Register and the active (high)
INTRPT output. All other system functions operate in their
normal manner, including the setting of the Line Status and
Modem Status Registers. The contents of the Interrupt
Enable Register are indicated in Table 3 and are described
below.
IER(0): When programmed high (IER(0) = Logic 1), IER(0)
enables Received Data Available interrupt.
IER(1): When programmed high (IER(1) = Logic 1), IER(1)
enables the Transmitter Holding Register Empty interrupt.
IER(2): When Programmed high (IER(2) = Logic 1), IER(2)
enables the Receiver Line Status interrupt.
IER(3): When programmed high (IER(3) = Logic 1), IER(3)
enables the Modem Status interrupt.
IER(4) - IER(7): These four bits of the IER are logic 0.
DR (LSR BIT 0)
ERBFI (IER BIT 0)
THRE (LSR BIT 5)
ETBEI (IER BIT 1)
OE (LSR BIT 1)
INTRPT
PIN 30
PE (LSR BIT 2)
FE (LSR BIT 3)
BI (LSR BIT 4)
ELSI (IER BIT 2)
DCTS (MSR BIT 0)
DDSR (MSR BIT 1)
TERI (MSR BIT 2)
DDCD (MSR BIT 3)
EDSSI (IER BIT 3)
FIGURE 1. 82C50A INTERRUPT CONTROL STRUCTURE
REGISTER
MNEMONIC
RBR
(Read Only)
THR
(Write Only)
DLL
DLM
IER
BIT 7
Data Bit 7
(MSB)
Data Bit 7
Bit 7
Bit 15
0
IIR
0
(Read Only)
TABLE 3. 82C50A ACCESSIBLE REGISTER SUMMARY
(NOTE: See Table 1 for how to access these registers.)
REGISTER BIT NUMBER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2
BIT 1
Data Bit 1
Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1
Bit 6
Bit 14
0
0
Bit 5
Bit 13
0
0
Bit 4
Bit 12
0
0
Bit 3
Bit 11
(EDSSI)
Enable
Modem
Status
Interrupt
0
Bit 2
Bit 10
(ELSI)
Enable
Receiver
Line
Status
Interrupt
Interrupt ID
Bit (1)
Bit 1
Bit 9
(ETBEI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
Interrupt ID
Bit (0)
LCR
MCR
(DLAB)
Divisor
Latch
Access
Bit
0
Set Break
Stick Parity
(EPS)
Even Parity
Select
(PEN)
Parity
Enable
0
0
Loop
Out 2
(STB)
Number
of Stop
Bits
Out 1
(WLSB1)
Word
Length
Select
Bit 1
(RTS)
Request
to Send
LSR
MSR
0
(DCD)
Data
Carrier
Detect
(TEMT)
Transmitter
Empty
(RI)
Ring
Indicator
(THRE)
Transmitter
Holding
Register
Empty
(DSR)
Data
Set
Ready
SCR
Bit 7
Bit 6
Bit 5
†LSB, Data Bit 0 is the first bit transmitted or received.
(BI)
Break
Interrupt
(CTS)
Clear
to
Send
Bit 4
(FE)
Framing
Error
(DDCD)
Delta
Data
Carrier
Detect
Bit 3
(PE)
Parity
Error
(TERI)
Trailing
Edge
Ring
Indicator
Bit 2
(OE)
Overrun
Error
(DDSR)
Delta
Data
Set
Ready
Bit 1
BIT 0
Data Bit 0
(LSB)†
Data Bit 0
Bit 0
Bit 8
(ERBFI)
Enable
Received
Data
Available
Interrupt
“0” 1F
Interrupt
Pending
(WLSB0)
Word
Length
Select
Bit 0
(DTR)
Data
Terminal
Ready
(DR)
Data
Ready
(DCTS)
Delta
Clear
to
Send
Bit 0
13
FN2958.5
August 24, 2006