82C50A_06 Datasheet, PDF (23/25 Pages) Intersil Corporation – CMOS Asynchronous

Timing Waveforms (Continued)
82C50A
DOSTR/DOSTR (WR MCR)
NOTE 1
RTS, DTR
OUT1, OUT2
ACTIVE
tMDO
(42)
ACTIVE
tMDO
(42)
CTS, DST, DCD
INTERRUPT
(43) tSIM
DISTR/DISTR (RD MSR)
NOTE 2
RI
NOTES:
1. See Write Cycle Timing.
2. See Read Cycle Timing.
tRIM
(44)
tSIM
(43)
ACTIVE
tRIM
(44)
tSIM
(43)
FIGURE 10. MODEM CONTROLS TIMING
23
FN2958.5
August 24, 2006