82C50A_06 Datasheet, PDF (22/25 Pages) Intersil Corporation – CMOS Asynchronous

Timing Waveforms (Continued)
82C50A
RCLK
SAMPLE CLK
SIN (RECEIVER INPUT DATA)
SAMPLE CLK
INTERRUPT
(DATA READY OR RCVR ERR)
DISTR/DISTR
(READ REC DATA BUFFER OR ROLSR)
NOTE 2
8 CLKS
tSCD (34)
PARITY
START
DATA BITS (5-8)
STOP
tSINT (35)
ACTIVE
tRINT
(36)
NOTES:
1. See Write Cycle Timing.
2. See Read Cycle Timing.
FIGURE 8. RECEIVER TIMING
SERIAL OUT
(SOUT)
INTERRUPT
(THRE)
DOSTR/DOSTR
(WR THR)
NOTE 1
DISTR/DISTR
(RD IIR)
NOTE 2
START
PARITY
START
(38)
tIRS
(37)
tHR
DATA (5-8)
(37)
tHR
STOP
(1-2)
tSTI (40)
(39)
tSI
tIR (41)
NOTES:
1. See Write Cycle Timing.
2. See Read Cycle Timing.
FIGURE 9. TRANSMITTER TIMING
22
FN2958.5
August 24, 2006