82C284883 Datasheet, PDF(6/9 Page) Intersil Corporation – Clock Generator and Ready Interface for 80C286 Processors

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82C284883 Datasheet, PDF (6/9 Pages) Intersil Corporation – Clock Generator and Ready Interface for 80C286 Processors

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82C284/883

Timing Waveforms

EFI

CLK

t16

t19

t15B

t18

t20

t15A t17

FIGURE 2. CLK AS A FUNCTION OF EFI

NOTE: The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown.

t16

CLK

t14

(SEE

t13

NOTE) t13

t14

RES

t24

RESET DEPENDS ON PREVIOUS

STATE OF RES

READY

t22

t21

NOTE: This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.

FIGURE 3. RESET AND READY TIMING AS A FUNCTION OF RES WITH S1, S0, ARDY + ARDYEN AND SRDY + SRDYEN HIGH

CLK

S1 â¢ S0

PCLK

SRDY + SRDYEN

ARDY + ARDYEN

READY

Ï1

Ï2

Ï1

Ï2

t5A

UNDEFINED IF THIS IS

FIRST BUS CYCLE

t11

t5B

t23

t25

t10

NOTE 1

t12

t11

t21

NOTE 2

t26

t12

t22

NOTES:

1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.

2. If SRDY + SRDYEN or ARDY + ARDYEN are active before and/or during the first bus cycle after RESET, READY may not be deasserted

until the falling edge of Ï2 of TS.

FIGURE 4. READY AND PCLK TIMING WITH RES HIGH

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