82C284883 Datasheet, PDF (4/9 Pages) Intersil Corporation – Clock Generator and Ready Interface for 80C286 Processors

82C284/883
TABLE 2. 82C284/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested. A.C. timings are referenced to 0.8V and 2.0V points of the signals as illustrated in datasheet wave-
forms, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
GROUP A
SUBGROUP
TEMPERATURE
10MHz
MIN MAX
12MHz
MIN MAX UNITS
NOTES:
1. VCC = 4.5V and 5.5V unless otherwise specified. CLK loading: CL = 100pF.
2. With the internal crystal oscillator using recommended crystal and capacitive loading; or with the EFI input meeting specifications t1 and t2.
The recommended crystal loading for CLK frequencies of 8MHz to 20MHz are 25pF from pin X1 to GND, and 15pF from pin X2 to GND; for
CLK frequencies from 20MHz to 25MHz the recommended loading is 15pF from pin X1 to GND, and 15pF from X2 to GND. These recom-
mended values are ±5pF and include all stray capacitance. Decouple VCC and GND as close to the 80C284/883 as possible.
3. This is an asychronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK edge.
4. The pull-up resistor value for the READY pin is 620Ω with the rated 150pF load.
5. t16 refers to any allowable CLK period.
6. When using a crystal with the recommended capacitive loading, CLK output HIGH and LOW times are guaranteed to meet 80C286 re-
quirements.
7. Measured from 1.0V on the CLK to 0.8V on the RES waveform for RES active, and to 4.2V on the RES waveform for RES inactive.
8. Input test waveform characteristics: VIL= 0.0V, VIH = 4.5V.
TABLE 3. 82C284/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
10MHz
12MHz
PARAMETER SYMBOL CONDITIONS
NOTES
TEMPERATURE
MIN MAX MIN MAX UNITS
Input Capacitance
CIN FREQ = 1MHz, All
1
measurements are
referenced to de-
vice GND
T_A = +25^oC
-
10
-
10
pF
EFI HIGH to CLK
LOW Delay
t15A
1, 2
-55^oC ≤ T_A ≤ +125^oC
-
30
-
25
ns
EFI LOW to CLK
HIGH Delay
t15B
1, 3
-55^oC ≤ T_A ≤ +125^oC
-
35
-
30
ns
CLK Rise Time
t19 1.0V to 3.6V,
CL = 100pF
1
-55^oC ≤ T_A ≤ +125^oC
-
8
-
8
ns
CLK Fall Time
t20 3.6V to 1.0V,
CL = 100pF
1
-55^oC ≤ T_A ≤ +125^oC
-
8
-
8
ns
X1 HIGH to CLK
t27
1, 4
-55^oC ≤ T_A ≤ +125^oC
-
35
-
30
ns
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
2. Measured from 3.2V on the EFI waveform to 1.0V on the CLK.
3. Measured from 0.8V on the EFI waveform to 3.6V on the CLK.
4. Measured from 3.6V on the X1 input to 3.6V on the CLK.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
4