82C284883 Datasheet, PDF (1/9 Pages) Intersil Corporation – Clock Generator and Ready Interface for 80C286 Processors

®
82C284/883
March 1997
Clock Generator and
Ready Interface for 80C286 Processors
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Generates System Clock for 80C286 Processors
• Generates System Reset Output from Schmitt Trigger
Input
- Improved Hysteresis
• Uses Crystal or External Signal for Frequency Source
- Dynamically Switchable Between Two Input
Frequencies
• Provides Local READY and MULTIBUS™ READY
Synchronization
• Static CMOS Technology
• Single +5V Power Supply
• Available in 18 Lead CERDIP Package
Description
The Intersil 82C284/883 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with hys-
teresis.
Ordering Information
PART NUMBER TEMP. RANGE PACKAGE PKG. NO.
MD82C284-12/883 -55^oC to +125^oC CERDIP F18.3
Functional Diagram
Pinout
82C284/883
(CERDIP)
TOP VIEW
ARDY 1
SRDY 2
SRDYEN 3
READY 4
EFI 5
F/C 6
X1 7
X2 8
GND 9
18 VCC
17 ARDYEN
16 S1
15 S0
14 NC
13 PCLK
12 RESET
11 RES
10 CLK
RES
X1
X2
EFI
F/C
ARDYEN
ARDY
SRDYEN
SRDY
RESET
SYNCHRONIZER
XTAL
OSC
MUX
SYNCHRONIZER
READY LOGIC
RESET
CLK
READY
S1
S0
PCLK GENERATOR
PCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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1
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FN2968.1