80C88_04 Datasheet, PDF (6/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
Pin Description (Continued)
The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions
which are unique to the maximum mode are described; all other pin functions are as described above.
MAXIMUM MODE SYSTEM
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
S0
26
O
STATUS: is active during clock high of T4, T1 and
S1
27
O
T2, and is returned to the passive state (1, 1, 1) ^{S2 S1 S0 CHARACTERISTICS}
S2
28
O
during T3 or during Tw when READY is HIGH. This 0 0 0 Interrupt Acknowledge
status is used by the 82C88 bus controller to gener-
0
0
1 Read I/O Port
ate all memory and I/O access control signals. Any
change by S2, S1 or S0 during T4 is used to ^{0 1 0 Write I/O Port}
indicate the beginning of a bus cycle, and the return
0
1
1 Halt
to the passive state in T3 or Tw is used to indicate
the end of a bus cycle.
1 0 0 Code Access
These signals are held at a high impedance logic 1 0 1 Read Memory
one state during “grant sequence”.
1 1 0 Write Memory
1 1 1 Passive
RQ/GT0,
31
RQ/GT1
30
LOCK
29
QS1, QS0 24, 25
I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the
local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0
having higher priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may
be left unconnected. The request/grant sequence is as follows (see RQ/GT Timing Sequence):
1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to
the 80C88 (pulse 1).
2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master
(pulse 2), indicates that the 80C88 has allowed the local bus to float and that it will enter the
“grant sequence” state at the next CLK. The CPUs bus interface unit is disconnected logically
from the local bus during “grant sequence”.
3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold”
request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU
then enters T4 (or T1 if no bus cycles pending).
Each master-master exchange of the local bus is a sequence of three pulses. There must be one
idle CLK cycle after bus exchange. Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it will release the local bus during
T4 of the cycle when all the following conjugations are met:
1. Request occurs on or before T2.
2. Current cycle is not the low bit of a word.
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle
apply with condition number 1 already satisfied.
O
LOCK: indicates that other system bus masters are not to gain control of the system bus while
LOCK is active (LOW). The LOCK signal is activated by the “LOCK” prefix instruction and remains
active until the completion of the next instruction. This signal is active LOW, and is held at a high
impedance logic one state during “grant sequence”. In Max Mode, LOCK is automatically generated
during T2 of the first INTA cycle and removed during T2 of the second INTA cycle.
O
QUEUE STATUS: provide status to allow external
tracking of the internal 80C88 instruction queue.
QS1 QS0 CHARACTERISTICS
The queue status is valid during the CLK cycle after
which the queue operation is performed. Note that
the queue status never goes to a high impedance
statue (floated).
0 0 No Operation
0 1 First Byte of Opcode from
Queue
1 0 Empty the Queue
1 1 Subsequent Byte from
Queue
-
34
O
Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during
a “grant sequence”.
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