80C88_04 Datasheet, PDF (23/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
Waveforms (Continued)
CLK
TCHSV (21)
S2, S1, S0 (EXCEPT HALT)
T1
T2
T3 _TW
T4
(SEE NOTE 24)
WRITE CYCLE
AD7-AD0
DEN
82C88
OUTPUTS
SEE NOTES 22, 23
AMWC OR AIOWC
MWTC OR IOWC
TCLAV ₍₂₃₎
TCLDV (33)
TCLAX (24)
TCVNV
(35)
(18) TCLML
(22)
TCLSH
DATA
TCLMH
(19)
(18)TCLML
TCLDX2
(34)
TCVNX (36)
TCLMH (19)
INTA CYCLE
A15-A8
(SEE NOTES 25, 26)
(25) TCLAZ
AD7-AD0
RESERVED FOR
CASCADE ADDR
(28) TSVMCH
MCE/PDEN
(30) TCLMCH
DT/R
82C88 OUTPUTS
SEE NOTES 22, 23, 25
INTA
TCLMCL ⁽³²⁾
(41)
TCHDTL
(18) TCLML
(6) TDVCL
POINTER
TCLDX1 (7)
(42) ^TCHDTH
TCVNV
(35)
DEN
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
AD7-AD0
A15-A8
S2, S1, S0
TCLAV
(23)
INVALID ADDRESS
(19) TCLMH
TCVNX
(36)
TCHSV
(21)
TCLSH
(22)
NOTES:
FIGURE 25. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)
22. Signals at 82C84A or 82C86 are shown for reference only.
23. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active
high 82C88 CEN.
24. Status inactive in state just prior to T4.
25. Cascade address is valid between first and second INTA cycles.
26. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is
shown for second INTA cycle.
23