80C88_04 Datasheet, PDF (10/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
Bus Operation
The 80C88 address/data bus is broken into three parts: the
lower eight address/data bits (AD0-AD7), the middle eight
address bits (A8-A15), and the upper four address bits (A16-
A19). The address/data bits and the highest four address
bits are time multiplexed. This technique provides the most
efficient use of pins on the processor, permitting the use of
standard 40 lead package. The middle eight address bits are
not multiplexed, i.e., they remain valid throughout each bus
cycle. In addition, the bus can be demultiplexed at the
processor with a single address latch if a standard, nonmulti-
plexed bus is desired for the system.
Each processor bus cycle consists of at least four CLK
cycles. These are referred to as T1, T2, T3 and T4. (See
Figure 5). The address is emitted from the processor during
T1 and data transfer occurs on the bus during T3 and T4. T2
is used primarily for changing the direction of the bus during
read operations. In the event that a “Not Ready” indication is
given by the addressed device, “wait” states (TW) are
inserted between T3 and T4. Each inserted “wait” state is of
the same duration as a CLK cycle. Periods can occur
between 80C88 driven bus cycles. These are referred to as
“idle” states (TI), or inactive CLK cycles. The processor uses
these cycles for internal housekeeping.
During T1 of any bus cycle, the ALE (Address latch enable)
signal is emitted (by either the processor or the 82C88 bus
controller, depending on the MN/MX strap). At the trailing
edge of this pulse, a valid address and certain status infor-
mation for the cycle may be latched.
Status bits S0, S1, and S2 are used by the bus controller, in
maximum mode, to identify the type of bus transaction
according to Table 2.
Status bits S3 through S6 are multiplexed with high order
address bits and are therefore valid during T2 through T4.
S3 and S4 indicate which segment register was used to this
bus cycle in forming the address according to Table 3.
S5 is a reflection of the PSW interrupt enable bit. S6 is
always equal to 0.
CLK
ALE
(4 + NWAIT) = TCY
(4 + NWAIT) = TCY
T1
T2
T3
TWAIT
T4
T1
T2
T3
TWAIT T4
GOES INACTIVE IN THE STATE
JUST PRIOR TO T4
S2-S0
ADDR
STATUS
ADDR
ADDR DATA
RD, INTA
READY
DT/R
A19-A16
S6-S3
A15-A8
A7-A0
BUS RESERVED ^D15-D0
FOR DATA IN
VALID
READY
WAIT
A19-A16
S6-S3
A15-A8
A7-A0
DATA OUT (D7-D0)
READY
WAIT
DEN
MEMORY ACCESS TIME
WP
FIGURE 18. BASIC SYSTEM TIMING
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