80C88_04 Datasheet, PDF (18/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
Waveforms
CLK (82C84A OUTPUT)
(30) TCHCTV
IO/M, SSO
A15-A8
T1
(1)
TCLCL
(3)
T2
TCH1CH2
(4)
TCHCL
T3
T4
(5) ^TW
TCL2CL1
(2)
TCLCH
A15-A8 (FLOAT DURING INTA)
TCHCTV
(30)
(17)
TCLAV
(17)
TCLAV
A19/S6-A16/S3
(23) TCLLH
ALE
RDY (82C84A INPUT)
SEE NOTE 9, 10
(26) TCLDV
(18) TCLAX
A19-A16
TLHLL
(22)
TLLAX
(25)
(24)
TCHLL
TAVAL
(39)
V_IH
V_IL
(12)
TRYLCL
S6-S3
TR1VCL (8)
TCLR1X (9)
(17)
TCLAV
READY (80C88 INPUT)
(11)
TCHRYX
AD7-AD0
READ CYCLE
(WR, INTA = V_OH)
RD
DT/R
DEN
AD7-AD0
(32) TAZRL
(19)
TCLAZ
(30)
TCHCTV
TCLRL
(33)
(29) TCVCTV
(10)
TRYHCH
(16)
TDVCL
(7)
TCLDX1
DATA IN
(34) TCLRH
TRHAV
(35)
TRLRH
(37)
(30)
TCHCTV
TCVCTX
(31)
NOTES:
FIGURE 22. BUS TIMING - MINIMUM MODE SYSTEM
9. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.
10. Signals at 82C84A are shown for reference only.
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