X9279_09 Datasheet, PDF (5/18 Pages) Intersil Corporation – Single Digitally-Controlled (XDCP™) Potentiometer

X9279
SERIAL DATA PATH
SERIAL
BUS
R_H
FROM INTERFACE
INPUT
CIRCUITRY
REGISTER 0
REGISTER 1
C
(DR0)
(DR1)
O
U
8
BANK_0 Only
8
PARALLEL
N
T
BUS
INPUT
E
R
REGISTER 2
(DR2)
REGISTER 3
(DR3)
WIPER
D
COUNTER
E
REGISTER
C
(WCR)
O
D
E
INC/DEC
R
IF WCR = 00[H] THEN R_W = R_L
IF WCR = FF[H] THEN R_W = R_H
UP/DN
LOGIC
UP/DN
MODIFIED SCK
CLK
R_L
R_W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Power-up and Down Recommendations.
There are no restrictions on the power-up or power-down
conditions of V_CC and the voltages applied to the
potentiometer pins provided that V_CC is always more
positive than or equal to V_H, V_L, and V_W, i.e., V_CC ≥ V_H, V_L,
V_W. The V_CC ramp rate specification is always in effect.
Serial Interface Description
Serial Interface
The X9279 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9279 will be
considered a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (see
Figure 2.
Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9279 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met (see Figure 2).
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 2).
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9279 will
respond with a final acknowledge (see Figure 2).
5
FN8175.4
September 23, 2009