X9279_09 Datasheet, PDF (10/18 Pages) Intersil Corporation – Single Digitally-Controlled (XDCP™) Potentiometer

X9279
Instruction Format
Read Wiper Counter Register (WCR)
S
Device Type
Device
Instruction
DR/Bank
Wiper Position
T
Identifier
Addresses
S
Opcode
Addresses S
(Sent by X9279 on SDA)
MS
A
A
A
AT
R ^{0 1 0 1 0 A 2 A 1 A 0} C ^{1 0 0 1 0 0 0 0} C ^{WC WC WC WC WC WC WC WC} C O
T
K
K ^{R7 R6 R5 R4 R3 R2 R1 R0} K P
Write Wiper Counter Register (WCR)
S
Device Type
Device
Instruction
DR/Bank
Wiper Position
T
Identifier
Addresses
S
Opcode
Addresses S
(Sent by Master on SDA)
SS
A
A
A
AT
R ^{0 1 0 1 0 A 2 A 1 A 0} C ^{1 0 1 0 0 0 0 0} C ^{WC WC WC WC WC WC WC WC} C O
T
K
K ^{R7 R6 R5 R4 R3 R2 R1 R0} K P
Read Data Register (DR)
S Device Type
Device
Instruction
DR/Bank
Wiper Position
T
Identifier
Addresses
S Opcode
Addresses
S
(Sent by X9279 on SDA)
MS
A
A
A
AT
R ^{0 1 0 1 0 A 2 A 1 A 0} C ^{1 0 1 1 RB RA P1 P0} C ^{WC WC WC WC WC WC WC WC} C O
T
K
K ^{R7 R6 R5 R4 R3 R2 R1 R0} K P
Write Data Register (DR)
Device Type
Device
Instruction
DR/Bank
Wiper Position
S
Identifier
Addresses
Opcode
Addresses
(Sent by Master on SDA)
T
S
S
SS
A ^{0 1 0 1 0 A 2 A 1 A 0} A ^{1 1 0 0 RB RA P1 P0} A ^{WC WC WC WC WC WC WC WC} A T
R
C
C ^{R7 R6 R5 R4 R3 R2 R1 R0} C O
T
K
K
KP
Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
Device Type
Device
Instruction
DR/Bank
T
Identifier
Addresses
S
Opcode
Addresses
SS
A
A
AT
R ^{0 1 0 1 0 A 2 A 1 A 0} C ^{1 1 1 0 RB RA 0 0} C O
T
K
KP
High-Voltage
Write Cycle
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
Device Type
Device
Instruction
T
Identifier
Addresses
S
Opcode
A
A
R⁰
1
0
1 0 A2
A1
A0
C^{1 1 0 1}
T
K
DR/Bank
Addresses
SS
AT
RB
RA
0 0 _CO
KP
Increment/Decrement Wiper Counter Register (WCR)
S Device Type
Device
Instruction
DR/Bank
Increment/Decrement
T
Identifier
Addresses
S
Opcode
Addresses S
(Sent by Master on SDA)
S
A _{0 1 0 1 0 A 2 A 1 A 0} A _{0 0 1 0 0 0 0 0} A _{I/D I/D . . . . I/D I/D} T
R
C
C
O
T
K
K
P
NOTES:
4. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
5. “A3 ~ A0”: stands for the device addresses sent by the master.
6. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
7. “I”: stands for the increment operation, SDA held high during active SCL phase (high).
8. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
10
FN8175.4
September 23, 2009