ISL6559 Datasheet, PDF (5/21 Pages) Intersil Corporation – Multi-Phase PWM Controller

ISL6559
Electrical Specifications Operating Conditions: VCC = 5V, T_A = 0°C to 70°C. Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
ERROR AMPLIFIER
Open-Loop Gain
Open-Loop Bandwidth
Slew Rate
Maximum Output Voltage
Source Current
R_L = 10kΩ to ground
C_L = 100pF, R_L = 10kΩ to ground
C_L = 100pF, Load = ±400mA
R_L = 10kΩ to ground
-
72
-
-
18
-
-
7.1
11
3.6
4.5
-
3.0
7.0
9.5
Sink Current
1.6
3.0
5.4
REMOTE-SENSE AMPLIFIER
Input Impedance
-
80
-
Bandwidth
-
20
-
Slew Rate
-
6
-
SENSE CURRENT
IOUT Accuracy
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 50µA
-5
-
5
ISEN Offset Voltage
-
6
-
Over-Current Trip Level
72
90
108
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
Under-Voltage Offset From VID
I_PGOOD = 4mA
VSEN Falling
-
-
0.4
320
350
420
Over-Voltage Threshold
VSEN Rising
2.08 2.13 2.20
OVP Voltage
I_OVP = 100mA, VCC = 5V
NOTE:
3. These parts are designed and adjusted for accuracy within the system tolerance
2.2
3.28
4.0
UNITS
dB
MHz
V/µs
V
mA
mA
kΩ
MHz
V/µs
%
mV
µA
V
mV
V
V
Functional Pin Description
ISL6559CB (28 LEAD SOIC)
TOP VIEW
ISL6559CR (32 LEAD QFN)
TOP VIEW
GND 1
OVP 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
OFS 8
COMP 9
FB 10
IOUT 11
VDIFF 12
VSEN 13
RGND 14
28 EN
27 FS/DIS
26 PGOOD
25 PWM4
24 ISEN4
23 ISEN1
22 PWM1
21 PWM2
32 31 30 29 28 27 26 25
VID2 1
24 PWM4
VID1 2
23 ISEN4
VID0 3
22 ISEN1
NC 4
21 PWM1
OFS 5
20 PWM2
20 GND ^{COMP 6}
19 GND
19 ISEN2
FB 7
18 ISEN2
18 ISEN3
17 PWM3
NC 8
17 ISEN3
9 10 11 12 13 14 15 16
16 VCC
15 GND
NC = NO CONNECT
GND
Bias and reference ground for the IC.
OVP
Over-voltage protection pin. This pin pulls to VCC and is
latched when an over-voltage condition is detected. Connect
this pin to the gate of an SCR or MOSFET tied across V_IN
and ground to prevent damage to a load device.
VID4, VID3, VID2, VID1, VID0
The state of these five inputs program the internal DAC,
which provides the reference voltage for output regulation.
Connect these pins to either open-drain or active pull-up
type outputs. Pulling these pins above 2.9V can cause a
reference offset inaccuracy.
OFS
Connecting a resistor between this pin and ground creates a
positive offset voltage which is added to the DAC voltage,
allowing easy implementation of load-line regulation. For no
offset, simply tie this pin to ground.
FB and COMP
The internal error amplifier inverting input and output
respectively. Connect the external R-C feedback
compensation network of the regulator to these pins.
IOUT
The current carried out of this pin is proportional to output
current and can be used to incorporate output voltage droop
5
FN9084.8
December 29, 2004