ISL6559 Datasheet, PDF (1/21 Pages) Intersil Corporation – Multi-Phase PWM Controller

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Data Sheet
December 29, 2004
ISL6559
FN9084.8
Multi-Phase PWM Controller
The ISL6559 provides core-voltage regulation by driving 2 to
4 interleaved synchronous-rectified buck-converter channels
in parallel. Interleaving the channel timing results in
increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6559 uses cost and space-saving r_DS(ON) sensing
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 50mV using a single external
resistor. The entire system is trimmed to ensure a system
accuracy of ±1% over temperature.
Outstanding features of this controller IC include
Dynamic VID^TM technology allowing seamless on-the-fly VID
changing without the need of any external components.
Output voltage “droop” or active voltage positioning is
optional. When employed, it allows the reduction in size and
cost of the output capacitors required to support load
transients. A threshold-sensitive enable input allows the use
of an external resistor divider for start-up coordination with
Intersil MOSFET drivers or any other devices powered from
a separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to crowbar the output voltage.
An optional second crowbar on V_IN, formed with an external
MOSFET or SCR gated by the OVP pin, is triggered when
an over-voltage condition is detected. Under-voltage
conditions are detected, but PWM operation is not disrupted.
Over-current conditions cause a hiccup-mode response as
the controller repeatedly tries to restart. After a set number
of failed startup attempts, the controller latches off. A power
good logic signal indicates when the converter output is
between the UV and OV thresholds.
Features
• Multi-Phase Power Conversion
- 2, 3 or 4 Phase Operation
• Active Channel Current Balancing
• Precision r_DS(ON) Current Sharing
- Lossless
- Low Cost
• Input Voltage: 12V or 5V Bias
• Precision CORE Voltage Regulation
- ± 1% System Accuracy Over Temperature
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID Technology
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 4MHz)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves PCB
efficiency and has a thinner profile
• Pb-Free Available (RoHS Compliant)
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
Pinouts
ISL6559CB (28 LEAD SOIC)
TOP VIEW
ISL6559CR (32 LEAD QFN)
TOP VIEW
GND 1
OVP 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
OFS 8
COMP 9
FB 10
IOUT 11
VDIFF 12
VSEN 13
RGND 14
28 EN
27 FS/DIS
26 PGOOD
32 31 30 29 28 27 26 25
25 PWM4 VID2 1
24 PWM4
24 ISEN4 VID1 2
23 ISEN4
23 ISEN1 VID0 3
22 ISEN1
22 PWM1
NC 4
21 PWM1
21 PWM2 _{OFS 5}
20 PWM2
20 GND
19 ISEN2
18 ISEN3
17 PWM3
COMP 6
19 GND
FB 7
18 ISEN2
NC 8
17 ISEN3
9 10 11 12 13 14 15 16
16 VCC
15 GND
NC = NO CONNECT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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