ISL6559 Datasheet, PDF (15/21 Pages) Intersil Corporation – Multi-Phase PWM Controller

ISL6559
loop. Select the values for these resistors based on the room
temperature r_DS(ON) of the lower MOSFETs; the full-load
operating current, I_FL; and the number of phases, N
according to Equation 19 (see also Figure 3).
R_ISEN
=
5-r--^D-0---S--×^{--(-1-O--0---N-–--6-)-}
I--_F----L-
N
(EQ. 19)
In certain circumstances, it may be necessary to adjust the
value of one or more of the ISEN resistors. This can arise
when the components of one or more channels are inhibited
from dissipating their heat so that the affected channels run
hotter than desired (see the section entitled Channel-Current
Balance). In these cases, chose new, smaller values of R_ISEN
for the affected phases. Choose R_ISEN,2 in proportion to the
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase.
R _{I S E N ,2}
=
R_ISEN
∆_-----T----2-
∆T₁
(EQ. 20)
In Equation 20, make sure that ∆T₂ is the desired temperature
rise above the ambient temperature, and ∆T₁ is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 20 is usually
sufficient, it may occasionally be necessary to adjust R_ISEN
two or more times to achieve perfect thermal balance between
all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R_FB in Figure 5.
Its value depends on the desired full-load droop voltage
(V_DROOP in Figure 5). If Equation 19 is used to select each
ISEN resistor, the load-line regulation resistor is as shown
in Equation 21.
R_FB
=
-V----^D----^R----^O-----^O----^P--
50 ×10^–6
(EQ. 21)
If one or more of the ISEN resistors was adjusted for thermal
balance, as in Equation 20, the load-line regulation resistor
should be selected according to Equation 22. Where I_FL is
the full-load operating current and R_ISEN(n) is the ISEN
resistor connected to the n^th ISEN pin.
∑ ^R_FB
=
----V-----^D----^R----^O-----^O----^P------
I_FL r_DS(ON)
R_ISEN(n)
n
(EQ. 22)
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
Since the system poles and zero are effected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
C₂ (OPTIONAL)
R_C
C_C
COMP
R_FB
+
V_DROOP
-
FB
IOUT
VDIFF
FIGURE 12. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6559 CIRCUIT
The feedback resistor, R_FB, has already been chosen as
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f₀. The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
15
FN9084.8
December 29, 2004