ISL6310_06 Datasheet, PDF (5/27 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6310
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage, V_BOOT . . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage, V_PHASE . . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V (<400ns, 20µJ) to 24V (<200ns, V_BOOT-PHASE = 12V)
Upper Gate Voltage, V_UGATE . . . . V_PHASE - 0.3V to V_BOOT + 0.3V
V_PHASE - 3.5V (<100ns Pulse Width, 2µJ) to V_BOOT + 0.3V
Lower Gate Voltage, V_LGATE. . . . . . . . GND - 0.3V to PVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance
θ_JA (°C/W) θ_JC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . . . .
35
5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%
Ambient Temperature (ISL6310CR, ISL6310CRZ) . . . 0°C to +70°C
Ambient Temperature (ISL6310IR, ISL6310IRZ) . . .-40°C to +85°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θ_JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
Gate Drive Bias Current
I_VCC; ENLL = high
I_PVCC; ENLL = high, all gate outputs open,
Fsw = 250kHz
VCC POR (Power-On Reset) Threshold
VCC Rising
VCC Falling
PVCC POR (Power-On Reset) Threshold
PVCC Rising
PVCC Falling
Oscillator Ramp Amplitude (Note 3)
Maximum Duty Cycle (Note 3)
V_P-P
CONTROL THRESHOLDS
ENLL Rising Threshold
ENLL Hysteresis
COMP Shutdown Threshold
COMP Falling
REFERENCE AND DAC
System Accuracy (DAC = 0.6V, 0.9V)
DROOP connected to IREF
System Accuracy (DAC = 1.2V, 1.50V)
DROOP connected to IREF
DAC Input Low Voltage (REF0, REF1)
DAC Input High Voltage (REF0, REF1)
External Reference (Note 3)
OFS Sink Current Accuracy (Negative Offset)
OFS Source Current Accuracy (Positive Offset)
R_OFS = 30kΩ from OFS to VCC
R_OFS = 10kΩ from OFS to GND
MIN
TYP
MAX UNITS
-
15
20
mA
-
1.5
3.0
mA
4.25
4.38
4.50
V
3.75
3.88
4.00
V
4.25
4.38
4.50
V
3.75
3.88
4.00
V
-
1.50
-
V
-
66.6
-
%
-
0.66
-
100
0.25
0.35
-
V
-
mV
0.5
V
-0.8
-
0.8
%
-0.5
-
0.5
%
-
-
0.4
V
0.8
-
-
V
0.6
-
1.75
V
47.5
50.0
52.5 μA
47.5
50.0
52.5 μA
5
FN9209.3
December 12, 2006