ISL6310_06 Datasheet, PDF (12/27 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6310
Voltage Regulation
In order to regulate the output voltage to a specified level, the
ISL6310 uses the integrating compensation network shown in
Figure 6. This compensation network insures that the steady
state error in the output voltage is limited only to the error in
the reference voltage (output of the DAC or the external
voltage reference) and offset errors in the OFS current
source, remote sense and error amplifiers. Intersil specifies
the guaranteed tolerance of the ISL6310 to include the
combined tolerances of each of these elements, except when
an external reference or voltage divider is used, then the
tolerances of these components has to be taken into account.
EXTERNAL CIRCUIT
R₂ C_{1 COMP}
DAC
ISL6310 INTERNAL CIRCUIT
VID DAC
REF
C_REF
FB
+
R₁
V_OFS
-
VDIFF
R_S1
+
V_OUT
VSEN
R_P1
-
RGND
-
V_DROOP
+
C_SUM
DROOP
IREF
ICOMP
ISUM
+
-
V_COMP
I_OFS ^{ERROR AMPLIFIER}
+
+
-
- ^DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
+
ISENSE
AMP-
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
The ISL6310 incorporates an internal differential remote
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the controller ground reference point,
resulting in a more accurate means of sensing output voltage.
Connect the load’s output sense pins to the non-inverting
input, VSEN, and inverting input, RGND, of the remote sense
amplifier. The droop voltage, V_DROOP, also feeds into the
remote sense amplifier. The remote sense output, V_DIFF, is
therefore equal to the sum of the output voltage, V_OUT, and
the droop voltage. V_DIFF is connected to the inverting input of
the error amplifier through an external resistor.
The output of the error amplifier, V_COMP, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
and regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 5. The internal and external
circuitry that controls voltage regulation is illustrated in
Figure 6.
V_OUT = V_REF ± V_OFS – V_DROOP
(EQ. 5)
Load-Line (Droop) Regulation
In some high current applications, a requirement on a
precisely controlled output impedance is imposed. This
dependence of output voltage on load current is often
termed “droop” or “load line” regulation.
The Droop is an optional feature in the ISL6310. It can be
enabled by connecting ICOMP pin to DROOP pin as shown
in Figure 6. To disable it, connect the DROOP pin to IREF
pin.
As shown in Figure 6, a voltage, V_DROOP, proportional to the
total current in all active channels, I_OUT, feeds into the
differential remote-sense amplifier. The resulting voltage at
the output of the remote-sense amplifier is the sum of the
output voltage and the droop voltage. As Equation 5 shows,
feeding this voltage into the compensation network causes
the regulator to adjust the output voltage so that it’s equal to
the reference voltage minus the droop voltage.
The droop voltage, V_DROOP, is created by sensing the
current through the output inductors. This is accomplished
by using a continuous DCR current sensing method.
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 7. The channel current,
I_L, flowing through the inductor, passes through the DCR.
Equation 6 shows the s-domain equivalent voltage, V_L,
across the inductor.
V_L(s) = I_L ⋅ (s ⋅ L + DCR)
(EQ. 6)
The inductor DCR is important because the voltage dropped
across it is proportional to the channel current. By using a
simple R-C network and a current sense amplifier, as shown
in Figure 7, the voltage drop across all of the inductors DCRs
can be extracted. The output of the current sense amplifier,
V_DROOP, can be shown to be proportional to the channel
currents I_L1 and I_L2, shown in Equation 7.
VDROOP(s)
=
⎛
⎝
--^s-----^â‹---^L---
DCR
+
1_⎠⎞
-------------------------------------------------------------------------
(s ⋅ RCOMP ⋅ CCOMP + 1)
⋅
R_{-----C-----O-----M-----P---}
RS
(EQ. 7)
⋅ (IL1 + IL2) ⋅ DCR
12
FN9209.3
December 12, 2006