ISL6310_06 Datasheet, PDF (21/27 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6310
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R₁, has already been chosen as
outlined in See “Load-Line (Droop) Regulation” on page 12.
Select a target bandwidth for the compensated system, F₀.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
Case 1:
-------------1--------------
2π ⋅ L ⋅ C
>
F₀
R₂
=
R₁
⋅
2----π_-----⋅_{---F----0----}⋅_{---V-----O----S----C-----}⋅_{--------L----}⋅_---C---
0.66 ⋅ V_IN
C₁
=
------------0---.--6---6-----^â‹---V-----^I-^N--------------
2π ⋅ V_OSC ⋅ R₁ ⋅ f₀
Case 2:
-------------1--------------
2π ⋅ L ⋅ C
≤
F₀
<
----------------1-----------------
2π ⋅ C ⋅ ESR
R₂ = R₁ ⋅ ^V-----O----^S----^C-----^â‹-0--⁽--.-26----^π_6---⁾--_â‹-²--V--^â‹--_I-F-_N---⁰²----^â‹---L-----^â‹---C---
C₁
=
----------------------------0---.--6---6-----^â‹---V----^I--^N-----------------------------
(2π)² ⋅ F₀₂ ⋅ V_OSC ⋅ R₁ ⋅ L ⋅ C
(EQ. 28)
Case 3:
F₀ > _2----π-----_â‹---C----1--_â‹---E----S-----R---
R₂ = R₁ ⋅ ^2--0--π--.-6---^â‹-6--F---_â‹-⁰--V--^â‹--_I-V-_N---^O--_â‹---^S_E----^C-S----^â‹_R---L--
C₂
=
----0---.--6---6-----^â‹---V----^I--^N-----^â‹---E-----S----R------^â‹-------C------
2π ⋅ V_OSC ⋅ R₁ ⋅ F₀ ⋅ L
In Equations 28, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent series
resistance of the bulk output filter capacitance; and V_OSC is
the peak-to-peak sawtooth signal amplitude as described in
the Electrical Specifications on page 5.
Once selected, the compensation values in Equations 28
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R₂. Slowly increase the
value of R₂ while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C₁ will not need adjustment. Keep the value of C₁ from
Equations 28 unless some performance issue is noted.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep
a position available for C₂, and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
Compensating the Converter operating without
Load-Line Regulation
The ISL6310 multi-phase converter operating without load
line regulation behaves in a similar manner to a voltage-
mode controller. This section highlights the design
consideration for a voltage-mode controller requiring external
compensation. To address a broad range of applications, a
type-3 feedback network is recommended (see Figure 21).
C₂
R₂
C₁
COMP
C₃
R₁
R₃
FB
VDIFF
ISL6310
FIGURE 21. COMPENSATION CONFIGURATION FOR
NON-LOAD-LINE REGULATED ISL6310 CIRCUIT
Figure 22 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a
small number of adjustments, to the multi-phase ISL6310
circuit. The output voltage (V_OUT) is regulated to the
reference voltage, VREF, level. The error amplifier output
(COMP pin voltage) is compared with the oscillator (OSC)
modified saw-tooth wave to provide a pulse-width modulated
wave with an amplitude of V_IN at the PHASE node. The
PWM wave is smoothed by the output filter (L and C). The
output filter capacitor bank’s equivalent series resistance is
represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a
DC gain, given by d_MAXV_IN/V_OSC, and shaped by the
output filter, with a double pole break frequency at F_LC and a
zero at F_CE. For the purpose of this analysis, L and DCR
represent the individual channel inductance and its DCR
divided by 2 (equivalent parallel value of the two output
inductors), while C and ESR represents the total output
capacitance and its equivalent series resistance.
F_LC
=
-------------¹--------------
2π ⋅ L ⋅ C
F_CE
=
----------------¹-----------------
2π ⋅ C ⋅ ESR
21
FN9209.3
December 12, 2006