ISL6310_06 Datasheet, PDF (11/27 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6310
transition low. During this time the current sense amplifier
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, I_L. This sensed current, I_SEN, is simply
a scaled version of the inductor current. The sample window
opens exactly 1/6 of the switching period, t_SW, after the
PWM transitions low. The sample window then stays open
the rest of the switching cycle until PWM transitions high
again, as illustrated in Figure 4.
The sampled current, at the end of the t_SAMPLE, is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
for channel current balance.
I_L
PWM
SWITCHING PERIOD
I_SEN
SAMPLING PERIOD
OLD SAMPLE
CURRENT
NEW SAMPLE
CURRENT
TIME
FIGURE 4. SAMPLE AND HOLD TIMING
The ISL6310 supports MOSFET r_DS(ON) current sensing to
sample each channel’s current for channel current balance.
The internal circuitry, shown in Figure 5 represents channel
n of an N-Channel converter. This circuitry is repeated for
each channel in the converter, but may not be active
depending on the status of the 2PH pin, as described in the
PWM Operation section.
I_n
ISEN
=
IL
x
-r--D-----S----⁽---O-----N-----⁾
RISEN
SAMPLE
&
HOLD
-
+
ISL6310 INTERNAL CIRCUIT
V_IN
CHANNEL N
UPPER MOSFET
I_L
ISEN(n)
R_ISEN
-
CHANNEL N
ILx rDS_(ON)
+
LOWER MOSFET
EXTERNAL CIRCUIT
FIGURE 5. ISL6310 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY FOR CURRENT BALANCE
The ISL6310 senses the channel load current by sampling
the voltage across the lower MOSFET r_DS(ON), as shown in
Figure 5. A ground-referenced operational amplifier, internal
to the ISL6310, is connected to the PHASE node through a
resistor, R_ISEN. The voltage across R_ISEN is equivalent to
the voltage drop across the r_DS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, I_L. The ISEN current is
sampled and held as described in the See “Current
Sampling” on page 10. From Figure 5, the following equation
for I_n is derived where I_L is the channel current.
I_n
=
I_L ⋅
r---_{D----S----(--O-----N----)}
R_ISEN
(EQ. 3)
Output Voltage Setting
The ISL6310 uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the REF0 and REF1 pins. The DAC decodes the 2-bit logic
signals into one of the discrete voltages shown in Table 1.
Each REF0 and REF1 pins are pulled up to an internal 1.2V
voltage by weak current sources (40μA current, decreasing
to 0 as the voltage at the REF0, REF1 pins varies from 0 to
the internal 1.2V pull-up voltage). External pull-up resistors
or active-high output stages can augment the pull-up current
sources, up to a voltage of 5V. The DAC pin must be
connected to REF pin through a 1 to 5kΩ resistor and a filter
capacitor (0.022μF) is connected between REF and GND.
The ISL6310 accommodates the use of external voltage
reference connected to REF pin if a different output voltage
is required. The DAC voltage must be set at least as high as
external reference. The error amp internal noninverting input
is the lower of REF or (DAC +300mV).
A third method for setting the output voltage is to use a
resistor divider (R_P1, R_S1) from the output terminal (V_OUT)
to VSEN pin to set the output voltage level as shown in
Figure 6. This method is good for generating voltages up to
2.3V (with the REF voltage set to 1.5V).
For this case, the output voltage can be obtained as follows:
V_OUT
=
V_REF
⋅
(_---R_{-----S---1-----+-----}R_{----P----1----})
R_P1
+−
V_OFS
–
V_DROOP
(EQ. 4)
It is recommended to choose resistor values of less than
500Ω for R_S1 and R_P1 resistors in order to get better output
voltage DC accuracy.
TABLE 1. ISL6310 DAC VOLTAGE SELECTION TABLE
REF1
REF0
DAC
0
0
0.600V
0
1
0.900V
1
0
1.200V
1
1
1.500V
11
FN9209.3
December 12, 2006