ISL6269_06 Datasheet, PDF (5/17 Pages) Intersil Corporation – High-Performance Notebook PWM Controller with Bias Regulator and Audio-Frequency Clamp

ISL6269
Functional Pin Descriptions
GND Pin
Bottom terminal pad of QFN package
Signal common of the IC. Unless otherwise stated, signals
are referenced to the GND pin, not the PGND pin.
VIN Pin-1 (Input)
The VIN pin measures the converter input voltage with
respect to the GND pin. VIN is a required input to the R³
PWM modulator. The VIN pin is also the input source for the
integrated +5V LDO regulator.
VCC Pin-2 (Output)
The VCC pin is the output of the integrated +5V LDO
regulator, which provides the bias voltage for the IC. The
VCC pin delivers regulated +5V whenever the EN pin is
pulled above V_ENTHR. For best performance the LDO
requires at least a 1µF MLCC decouple capacitor to the
GND pin.
FCCM Pin-3 (Logic)
The FCCM pin configures the controller to operate in forced-
continuous-conduction-mode (FCCM) or diode-emulation-
mode (DEM.) DEM is disabled when the FCCM pin is pulled
above the rising threshold voltage V_FCCMTHR, and DEM is
enabled when the FCCM pin is pulled below the falling
threshold voltage V_FCCMTHF.
EN Pin-4 (Logic)
The EN pin is the on/off switch of the IC. When the EN pin is
pulled above the rising threshold voltage V_ENTHR, V_CC will
ramp up and begin regulation. The soft-start sequence
begins once V_CC ramps above the power-on reset (POR)
rising threshold voltage V_CCTHR. When the EN pin is pulled
below the falling threshold voltage V_ENTHF, PWM
immediately stops and V_CC decays below the POR falling
threshold voltage V_CCTHF, at which time the IC turns off.
COMP Pin-5 (Signal)
The COMP pin is the output of the control-loop error
amplifier. Loop compensation components connect from the
COMP pin to the FB pin.
FB Pin-6 (Signal)
The FB pin is the inverting input of the control loop error
amplifier. The converter will regulate to 600mV at the FB pin
with respect to the GND pin. Scale the desired output
voltage to 600mV with a voltage divider network made from
resistors R_TOP and R_BOTTOM. Loop compensation
components connect from the FB pin to the COMP pin.
FSET Pin-7 (Signal)
The FSET pin programs the PWM switching frequency of the
converter. Connect a resistor R_FSET and a 10nF capacitor
C_FSET from the FSET pin to the GND pin.
VO Pin-8 (Input)
The VO pin makes a direct measurement of the converter
output voltage used exclusively by the R³ PWM modulator.
The VO pin should be connected to the top of feedback
resistor R_TOP at the converter output. Refer to Figure 1,
Typical Application Schematic.
ISEN Pin-9 (Input)
The ISEN pin is the input to the overcurrent protection (OCP)
and short-circuit protection (SCP) circuits. Connect a resistor
R_SEN between the ISEN pin and the PHASE pin. Select the
value of R_SEN that will force the ISEN pin to source the I_SEN
threshold current I_OC when the peak inductor current
reaches the desired OCP setpoint. The SCP threshold
current I_SC is fixed at twice the OCP threshold current I_OC
PGND Pin-10
The PGND pin should be connected to the source of the low-
side MOSFET, preferably with an isolated path that is in
parallel with the trace connecting the LG pin to the gate of
the MOSFET. The PGND pin is an isolated path used
exclusively to conduct the turn-off transient current that flows
out the PGND pin, through the gate-source capacitance of
the low-side MOSFET, into the LG pin, and back to the
PGND pin through the pull-down resistance of the LG driver.
The adaptive shoot-through protection circuit, measures the
low-side MOSFET gate voltage with respect to the PGND
pin, not the GND pin.
LG Pin-11 (Output)
The LG pin is the output of the low-side MOSFET gate
driver. Connect to the gate of the low-side MOSFET.
PVCC Pin-12 (Input)
The PVCC pin is the input voltage for the low-side MOSFET
gate driver LG. Connect a +5V power source to the PVCC
pin with respect to the GND pin, a 1µF MLCC bypass
capacitor needs to be connected from the PVCC pin to the
PGND pin, not the GND pin. The VCC output may be used
for the PVCC input voltage source. Connect the VCC pin to
the PVCC pin through a low-pass filter consisting of a
resistor and the PVCC bypass capacitor. Refer to Figure 1,
Typical Application Schematic.
BOOT Pin-13 (Input)
The BOOT pin is the input voltage for the high-side MOSFET
gate driver UG. An MLCC capacitor C_BOOT is connected
between the BOOT pin and the PHASE pin, the return
current path for the UG MOSFET driver. Capacitor C_BOOT is
charged from the voltage source at the PVCC pin via the
internal diode D_BOOT each time the PHASE pin drops below
PVCC minus diode D_BOOT forward voltage drop V_F.
UG Pin-14 (Output)
The UG pin is the output of the high-side MOSFET gate
driver. Connect to the gate of the high-side MOSFET.
5
FN9177.1
August 7, 2006