ISL6269_06 Datasheet, PDF (12/17 Pages) Intersil Corporation – High-Performance Notebook PWM Controller with Bias Regulator and Audio-Frequency Clamp

ISL6269
Undervoltage
When an UVP fault is detected, the ISL6269 undervoltage
protection circuit will pull the PGOOD pin low and latch off
the converter. The UVP fault occurs when the voltage at the
FB pin relative to the GND pin, has fallen below the under-
voltage threshold V_UV. The fault will remain latched until the
EN pin is pulled below V_ENF or if the voltage at the VIN is
reduced to the extent that V_CC has fallen below the POR
V_CCF threshold.
Over-Temperature
When an OTP fault is detected, the ISL6269 over-
temperature protection circuit suspends PWM, but will not
affect the PGOOD pin, or latch off the converter. The over-
temperature protection circuit measures the temperature of
the silicon and activates when the rising threshold
temperature T_OTR has been exceeded. The PWM remains
suspended until the silicon temperature falls below the
temperature hysteresis T_OTHYS at which time normal
operation is resumed. All other protection circuits will
function normally during OTP however, since PWM is
inhibited, it is likely that the converter will immediately
experience an undervoltage fault, latch off, and pull PGOOD
low. If the EN pin is pulled below V_ENF or if the voltage at the
VIN is reduced to the extent that V_CC has fallen below the
POR V_CCF threshold, normal operation will resume
however, the temperature hysteresis T_OTHYS is reset.
PGOOD
The PGOOD pin connects to three open drain MOSFETS
each of which has a different r_DS(ON). Consult the Electrical
Specifications Table for the pull-down resistance of PGOOD
for the corresponding fault. The PGOOD pin is high
impedance whenever V_CC is below the rising POR threshold
V_OVR, the falling POR threshold V_OVF, after delay T_SS
elapses, without an OVP, OCP, SCP, or UVP fault. This fault-
identification capability is a useful tool for trouble-shooting.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
IC Off
Open
Soft Start
95Ω
Undervoltage Fault
95Ω
Overvoltage Fault
60Ω
Overcurrent Fault
30Ω
Component Selection
Programming the Output Voltage
When the converter is in regulation there will be 600mV from
the FB pin to the GND pin. Connect a two-resistor voltage
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 600mV with respect to the
GND pin when the converter is regulating at the desired
output voltage.
Programming the output voltage can be written as:
V_REF
=
V
O
U
T
•
------------^R----^B----^O-----^T---^T----^O----^M---------------
R_TOP + R_BOTTOM
(EQ. 5)
Where:
- V_OUT is the desired output voltage of the converter.
- V_REF is the voltage that the converter regulates to at the
FB pin.
- R_TOP is the voltage-programming resistor that connects
from the FB pin to the VO pin. It is usually chosen to set
the gain of the control-loop error amplifier. It follows that
R_BOTTOM will be calculated based upon the already
selected value of R_TOP.
- R_BOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin.
Calculating the value of R_BOTTOM can now be written as:
R_BOTTOM
=
--^V----^R----^E----^F----^•---^R----^T----^O----^P----
V_OUT – V_REF
(EQ. 6)
Programming the PWM Switching Frequency
The PWM switching frequency F_OSC is programmed by the
resistor R_FSET that is connected from the FSET pin to the
GND pin. Programming the approximate PWM switching
frequency can be written as:
F_OSC
=
-----------------------------¹------------------------------
60 • R_FSET • [1×10^–12]
(EQ. 7)
Estimating the value of R_FSET can now be written as:
R_FSET
=
---------------------------¹----------------------------
60 • F_OSC • [1×10^–12]
(EQ. 8)
Where:
- F_OSC is the PWM switching frequency.
- R_FSET is the F_OSC programming resistor.
- 60 x [1 x 10^-12] is a constant.
Selection of the LC Output Filter
The duty cycle of a buck converter is ideally a function of the
input voltage and the output voltage. This relationship can be
written as:
D(V_IN)
=
V_{-----O----U----T--}
V_IN
(EQ. 9)
Where:
- D is the PWM duty cycle.
- V_IN is the input voltage to be converted.
- V_OUT is the regulated output voltage of the converter.
The output inductor peak-to-peak ripple current can be
written as:
I_PP
=
V_{-----O----U----T-----}•_--[_---1_{-----–----}D_-----(_--V_{----I--N-----})_--]
F_OSC • L_O
(EQ. 10)
12
FN9177.1
August 7, 2006