ISL6269_06 Datasheet, PDF (15/17 Pages) Intersil Corporation – High-Performance Notebook PWM Controller with Bias Regulator and Audio-Frequency Clamp

ISL6269
Pin 5 (COMP)
The loop compensation components connect from the
COMP pin to the FB pin. Place the components close to the
FB pin to make the traces as short as possible.
Pin 6 (FB)
There is usually a resistor divider connecting the output
voltage of the converter to the FB pin. The correct layout
should bring the output voltage from the regulation point to
the FB pin with kelvin traces. The input impedance of the FB
pin is high, so place the resistor divider close to the pin,
keeping the high impedance trace short.
Pin 7 (FSET)
This pin requires a quiet environment. The resistor R_FSET
and capacitor C_FSET should be placed directly adjacent to
this pin. Keep fast moving nodes away from this pin.
Pin 8 (VO)
The VO pin should be connected to the Kelvin traces at the
FB voltage divider.
Pin 9 (ISEN)
The ISEN trace should be routed away from the traces and
components connected to the FB pin, COMP pin, and FSET
pin.
Pin 10 (PGND)
This is the pull-down return path for the LG low-side
MOSFET gate drive. This should be an isolated low-
resistance, low-inductance trace that connects to the source
of the low-side MOSFET.
Pin 11 (LG)
Connect to the gate terminal of the low-side MOSFET. The
signal going through this trace is both high dv/dt and high
di/dt, with high peak charging and discharging current. Route
this trace in parallel with the trace from the PGND pin. These
two traces should be short, wide, and away from other
traces. There should be no other weak signal traces in
parallel with these traces on any layer.
Pin 12 (PVCC)
A ceramic decoupling capacitor connects from the PVCC pin
to the PGND pin, not the GND pin. Closely place the
capacitor on the same side of the board as the ISL6269 IC.
Pin 13 (BOOT)
The di/dt and dv/dt of this pin are as high as that of the LG
pin, UG pin, and the PHASE pin; therefore, the traces should
be as short as possible.
Pin 14 (UG)
Connect to the gate terminal of the high-side MOSFET. The
signal going through this trace is both high dv/dt and high
di/dt, with high peak charging and discharging current. Route
this trace in parallel with the trace from the PHASE pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
parallel with these traces on any layer.
Pin 15 (PHASE)
Connect to the low-side MOSFET drain terminal. The phase
node has a very high dv/dt with a voltage swing from the input
voltage to ground. This trace should be short, and positioned
away from other weak signal traces.
Pin 16 (PGOOD)
A very robust pin. Treat as a typical logic signal.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. If
ringing is excessive, it could easily affect current sample
information. It would be best to limit the size of the PHASE
node copper in strict accordance with the current and
thermal management of the application.
Identify the Power and Signal Ground
The input and output capacitors of the converter, the source
terminal of the low-side MOSFET, and the PGND pin should
be closely connected to the power ground. The other
components should connect to signal ground. Signal and
power ground are tied together at the negative terminal of
the output capacitors.
Decoupling Capacitor for Switching MOSFET
Ceramic capacitors should be closely connected to the drain
side of the high-side MOSFET, and the source of the low-
side MOSFET. This capacitor reduces the amplitude of the
turn-off voltage spike.
Control Loop
The control loop model of the ISL6269 is partitioned into
function blocks consisting of:
- The Duty cycle to Vo transfer function G_vd(s) which is
determined by the value of the output power
components, input voltage, and output voltage.
- The Vcomp to Duty cycle transfer function F_m(s) which
is determined by the PWM frequency, input voltage,
output voltage, resistor R_FSET, and capacitor C_FSET.
- The product of the G_vd(s) and F_m(s) transfer functions
is expressed as the Vcomp to Vo transfer function
G_vovc(s).
- The type-two compensation network G_comp(s) that
connects across the COMP and FB pins.
- The product of the G_comp(s) and G_vovc(s) transfer
functions is expressed as the loop transfer function T(s).
15
FN9177.1
August 7, 2006