ISL6269_06 Datasheet, PDF (14/17 Pages) Intersil Corporation – High-Performance Notebook PWM Controller with Bias Regulator and Audio-Frequency Clamp

ISL6269
assumed to be the conduction loss only and can be written
as:
P_CONLS⋅D(V_IN) ≈ [I_LOAD]² • r_DS(ON)LS • [1 – D(V_IN)] (EQ. 15)
For the high-side MOSFET, its conduction loss can be
written as:
P_CONHS⋅D(V_IN) = [I_LOAD]² • r_DS(ON)HS • D(V_IN)
(EQ. 16)
For the high-side MOSFET, its switching loss can be written
as:
P_SWHS(V_IN)
=
V_{-----I--N----}•_---I_{--V----A----L----}•_--T_{----O-----N----}•_---F_{----O----S----C-- + -}V_----I--N----•_---I_{--P----E----A----K----}•_---T_{----O----F----F----}•_---F_{---O-----S----C--}
2
2
(EQ. 17)
The peak and valley current of the inductor can be obtained
based on the inductor peak-to-peak current and the load
current. The turn-on and turn-off time can be estimated with
the given gate driver parameters in the Electrical
Specification Table.
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor can be written as:
C_BOOT
=
---------^Q-----^g---------
∆V_BOOT
(EQ. 18)
Where:
- Q_g is the total gate charge required to switch the
high-side MOSFET
- ∆V_BOOT, is the maximum allowed voltage decay across
the boot capacitor each time the MOSFET is switched
on
As an example, suppose the high-side MOSFET has a total
gate charge Q_G, of 25nC at V_GS = 5V, and a ∆V_BOOT of
200mV. The calculated bootstrap capacitance is 0.125µF;
select at least the first standard component value of greater
capacitance than calculated, that being 0.15µF. Use an X7R
or X5R ceramic capacitor.
Layout Considerations
Power and Signal Layer Placement on the PCB
As a general rule, power layers should be adjacent to one
another towards one side of the board, with signal layers
adjacent to one another towards the opposite side of the
board. For example, prospective layer arrangement on a 4
layer board is shown below:
1. Top Layer: ISL6269 signal lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
It is a good engineering practice to separate the power
conductors from the signal conductors. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces. The loop formed by the
bottom MOSFET, output inductor, and output capacitor,
should be very small.
A guard-ring placed around high impedance inputs FB and
FSET is recommended.
Component Placement
Power MOSFETs should be placed close to the IC so that
VIN, LG, UG, PHASE, BOOT, and ISEN traces can be short.
Place components in such a way that the area near the
FSET, FB, COMP, and VO pins avoid traces with high dv/dt
and di/dt, such as gate signals and phase node signals.
V_IN
-
+
-
V_o
+
L_o
L_o
FIGURE 5. TYPICAL POWER COMPONENT PLACEMENT
Signal Ground and Power Ground Connection
The bottom of the ISL6269 QFN package is the analog and
logic ground terminal (GND) of the IC. Connect the GND pad
of the ISL6269 to the signal ground layer of the pcb using at
least five vias, for a robust thermal and electrical conduction
path. The best tie-point between the signal ground and the
power ground is at the negative side of the output capacitors
that is not in the return path of the inductor ripple current
flowing through the output capacitors.
Pin 1 (VIN)
The VIN pin should be connected to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
Pin 2 VCC
For best performance the LDO requires at least a 1µF MLCC
decouple capacitor connected from the VCC pin to the GND
pin.
Pin 3 (FCCM) and Pin 4 (EN)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
14
FN9177.1
August 7, 2006