ISL6269_06 Datasheet, PDF (13/17 Pages) Intersil Corporation – High-Performance Notebook PWM Controller with Bias Regulator and Audio-Frequency Clamp

ISL6269
Where:
- I_PP is the peak-to-peak output inductor ripple current.
- F_OSC is the PWM switching frequency.
- L_O is the nominal value of the output inductor.
A typical step-down DC/DC converter will have an I_PP of
20% to 40% of the nominal DC output load current. The
value of I_PP is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the
resistance the inductor winding, DCR. The DC copper loss of
the inductor can be estimated by:
P_COPPER = [I_LOAD]² • DCR
(EQ. 11)
The inductor copper loss can be significant in the total
system power loss. Attention has to be given to the DCR
selection. Another factor to consider when choosing the
inductor is its saturation characteristics at elevated
temperature. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance C_O
into which ripple current I_PP can flow. Current I_PP develops a
corresponding ripple voltage V_PP across C_O, which is the
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
the capacitor. These two voltages can be written as:
∆V_ESR = I_PP • ESR
(EQ. 12)
and
∆V_C
=
-------------^I--^P----^P---------------
8 • C_O • F_OSC
(EQ. 13)
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be
paralleled to adjust the ESR to achieve the required V_PP.
The inductance of the capacitor can cause a brief voltage dip
when the load transient has an extremely high slew rate.
Low inductance capacitors constructed with reverse
package geometry are available.
A capacitor dissipates heat as a function of RMS current. Be
sure that I_PP is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated
RMS current. Take into account that the specified value of a
capacitor can drop as much as 50% as the DC voltage
across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. For most cases, the RMS current
rating requirement for the input capacitors of a buck
regulator is approximately 1/2 the DC output load current.
The maximum RMS current required by the regulator can be
approximated through the following equation:
I_RMS = I_LOAD • [D] – [D]²
(EQ. 14)
Where:
- D is the converter duty cycle.
- I_RMS is the input capacitance RMS ripple current.
- I_LOAD is the converter output DC load current.
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
terminal of the high-side MOSFET and the source terminal
of the low-side MOSFET, in order to reduce the voltage
ringing created by the switching current across parasitic
circuit elements.
MOSFET Selection and Considerations
Typically, MOSFETS cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETS used in the power conversion stage of the
converter should have a maximum V_DS rating that exceeds
the upper voltage tolerance of the input power source, and
the voltage spike that occurs when the MOSFET switches
off. Placing a low ESR ceramic capacitor as close as
practical across the drain of the high-side MOSFET and the
source of the low-side MOSFET will reduce the amplitude of
the turn-off voltage spike.
The MOSFET input capacitance C_ISS, and on-state drain to
source resistance r_DS(ON), are to an extent, inversely
related; reduction of r_DS(ON) typically results in an increase
of C_ISS. These two parameters affect the efficiency of the
converter in different ways. The r_DS(ON) affects the power
loss when the MOSFET is completely turned on and
conducting current. The C_ISS affects the power loss when
the MOSFET is actively switching. Switching time increases
as C_ISS increases. When the MOSFET switches it will briefly
conduct current while the drain to source voltage is still
present. The power dissipation during this time is substantial
so it must be kept as short as practical. Often the high-side
MOSFET and the low-side MOSFET are different devices
due to the trade-offs that have to be made between C_ISS
and r_DS(ON).
The low-side MOSFET power loss is dominated by r_DS(ON)
because it conducts current for the majority of the PWM
switching cycle; the r_DS(ON) should be small. The switching
loss is small for the low-side MOSFET even though C_ISS is
large due to the low r_DS(ON) of the device, because the drain
to source voltage is clamped by the body diode. The
high-side MOSFET power loss is dominated by C_ISS
because it conducts current for the minority of the PWM
switching cycle; the C_ISS should be small. The switching
loss of the high-side MOSFET is large compared to the low-
side MOSFET because the drain to source voltage is not
clamped. For the lower MOSFET, its power loss can be
13
FN9177.1
August 7, 2006