ISL1218 Datasheet, PDF (5/21 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM

ISL1218
SDA vs SCL Timing
t_F
t_HIGH
t_LOW
t_R
SCL
t_SU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t_SU:DAT
t_HD:STA
t_HD:DAT
t_AA
t_DH
t_SU:STO
t_BUF
Symbol Table
WAVEFORM
INPUTS
Must be steady
OUTPUTS
Will be steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not Known
N/A
Center Line is
High Impedance
5
FN6313.0
June 22, 2006