ISL1218 Datasheet, PDF (12/21 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM

ISL1218
NOTE: Writing to register 08h has restrictions. If V_BAT>V_DD, then no
byte writes to register 08h are allowed, only page writes beginning
with register 07h. If V_DD>V_BAT, then a byte write to register 08h IS
allowed, as well as page writes.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/F_OUT pin. See
Table 4 for frequency selection. When the frequency mode is
enabled, it will override the alarm mode at the IRQ/F_OUT pin.
TABLE 4. FREQUENCY SELECTION OF F_OUT PIN
FREQUENCY,
F_OUT
UNITS
0
Hz
FO3
0
FO2 FO1 FO0
0
0
0
32768
Hz
0
0
0
1
4096
Hz
0
0
1
0
1024
Hz
0
0
1
1
64
Hz
0
1
0
0
32
Hz
0
1
0
1
16
Hz
0
1
1
0
8
Hz
0
1
1
1
4
Hz
1
0
0
0
2
Hz
1
0
0
1
1
Hz
1
0
1
0
1/2
Hz
1
1/4
Hz
1
1/8
Hz
1
1/16
Hz
1
0
1
1
1
0
0
1
0
1
1
1
0
1/32
Hz
1
1
1
1
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the F_OUT/IRQ pin during battery
backup mode (i.e. V_BAT power source active). When the
FOBATB is set to “1” the F_OUT/IRQ pin is disabled during
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the F_OUT/IRQ pin is enabled
during battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
V_BAT supply will be used when V_DD < V_BAT - V_BATHYS and
V_DD < V_TRIP. With LPMODE = “1”, the device will be in low
power mode and the V_BAT supply will be used when
V_DD < V_BAT - V_BATHYS. There is a supply current saving of
about 600nA when using LPMODE = “1” with V_DD = 5V.
(See Typical Performance Curves: I_DD vs V_CC with
LPMODE ON and OFF.)
It should be noted that any writes to the LPMODE bit that
may put the device into Low Power Mode should be avoided
if V_DD<V_BAT, as the device will no longer communicate over
the I²C interface (until V_DD rises above V_BAT).
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/F_OUT pin when the RTC is
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/F_OUT pin will be
tied low until the ALM status bit is cleared to “0”.
IM BIT
0
1
INTERRUPT/ALARM FREQUENCY
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR<5:0>)
X1
C_X1
X2
C_X2
CRYSTAL
OSCILLATOR
FIGURE 11. DIAGRAM OF ATR
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to -94
to +140ppm of total adjustment.
12
FN6313.0
June 22, 2006