ISL1218 Datasheet, PDF (15/21 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM

ISL1218
The ISL1218 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL1218 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE ISL1218
WRITE
S
T
A ^{IDENTIFICATION}
R
BYTE
T
ADDRESS
BYTE
11011110 0000
A
A
C
C
K
K
DATA
BYTE
S
T
O
P
A
C
K
FIGURE 14. BYTE WRITE SEQUENCE
15
FN6313.0
June 22, 2006