ISL1218 Datasheet, PDF (4/21 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM

ISL1218
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
Hysteresis
V_OL
Cpin
f_SCL
t_IN
t_AA
t_BUF
PARAMETER
SDA and SCL Input Buffer Hysteresis
TEST CONDITIONS
SDA Output Buffer LOW Voltage,
Sinking 3mA
SDA and SCL Pin Capacitance
SCL Frequency
T_A = 25°C, f = 1MHz, V_DD = 5V,
V_IN = 0V, V_OUT = 0V
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec
and SCL Inputs
is suppressed.
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V_DD,
Valid
until SDA exits the 30% to 70% of V_DD
window.
Time the Bus Must be Free before the
Start of a New Transmission
SDA crossing 70% of V_DD during a
STOP condition, to SDA crossing 70%
of V_DD during the following START
condition.
MIN
0.05 x
V_DD
0
TYP
(Note 5)
1300
MAX
0.4
10
400
50
900
UNITS NOTES
V
V
pF
kHz
ns
ns
ns
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
t_SU:DAT
Input daTa Setup Time
t_HD:DAT
Input Data Hold Time
t_SU:STO
STOP Condition Setup Time
t_HD:STO
t_DH
STOP Condition Hold Time
Output Data Hold Time
t_R
SDA and SCL Rise Time
Measured at the 30% of V_DD crossing. 1300
Measured at the 70% of V_DD crossing. 600
SCL rising edge to SDA falling edge.
600
Both crossing 70% of V_DD.
From SDA falling edge crossing 30% of 600
V_DD to SCL falling edge crossing 70%
of V_DD.
From SDA exiting the 30% to 70% of
100
V_DD window, to SCL rising edge
crossing 30% of V_DD
From SCL falling edge crossing 30% of
0
V_DD to SDA entering the 30% to 70%
of V_DD window.
From SCL rising edge crossing 70% of 600
V_DD, to SDA rising edge crossing 30%
of V_DD.
From SDA rising edge to SCL falling
600
edge. Both crossing 70% of V_DD.
From SCL falling edge crossing 30% of
0
V_DD, until SDA enters the 30% to 70%
of V_DD window.
From 30% to 70% of V_DD
20 +
0.1 x Cb
ns
ns
ns
ns
ns
900
ns
ns
ns
ns
300
ns
6
t_F
SDA and SCL Fall Time
From 70% to 30% of V_DD
20 +
0.1 x Cb
300
ns
6
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
6
Rpu
SDA and SCL Bus Pull-up Resistor Maximum is determined by t_R and t_F.
1
Off-chip
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
kΩ
6
NOTES:
2. IRQ and F_OUT Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the V_{DD SR-} specification must be followed.
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. These are I²C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
7. A write to register 08h should only be done if V_DD > V_BAT, otherwise the device will be unable to communicate using I²C.
4
FN6313.0
June 22, 2006