HMU16JC-35 Datasheet, PDF (5/13 Pages) Intersil Corporation – 16 x 16-Bit CMOS Parallel Multipliers

HMU16, HMU17
Functional Description
The HMU16/HMU17 are high speed 16 x 16-bit multipliers
designed to perform very fast multiplication of two 16-bit
binary numbers. The two 16-bit operands (X and Y) may be
independently specified as either two's complement or
unsigned magnitude format by the two's complement
controls (TCX and TCY). When either of these control lines
is LOW, the respective operand is treated as an unsigned
16-bit value; and when it is HIGH, the operand is treated as
a signed value represented in two's complement format. The
operands along with their respective controls are latched at
the rising edge of the associated clock signal. The HMU16
accomplishes this through the use of independent clock
inputs for each of the Input Registers (CLKX and CLKY),
while the HMU17 utilizes a single clock signal (CLK) along
with the X and Y register enable inputs (ENX and ENY).
Input controls are also provided for rounding and format
adjustment of the 32-bit product. The Round input (RND) is
provided to accommodate rounding of the most significant
portion of the product by adding one to the Most Significant
Bit (MSB) of the LSP Register. The position of the MSB is
dependent on the state of the Format Adjust Control (see Pin
Descriptions and Multiplier Input/Output Format Tables). The
Round input is latched into the RND Register whenever
either of the input registers is clocked. The Format Adjust
control (FA) allows the product output to be formatted. When
the FA control is HIGH, a full 32-bit product is output; and
when FA is LOW, a left-shifted 31-bit product is output with
the sign bit replicated in bit position 15 of the LSP. The FA
control must be HIGH for unsigned magnitude, and mixed
mode multiplication operations. It may be LOW for certain
two's complement integer and fractional operations only (see
Multiplier Input/ Output Formats Table).
The HMU16/HMU17 multipliers are equipped with two 16-bit
Output Registers (MSP and LSP) which are provided to hold
the most and least significant portions of the resultant
product respectively. The HMU16 uses independent clocks
(CLKM and CLKL) for latching the two output registers, while
the HMU17 uses a single clock input (CLK) along with the
Product Latch Enable (ENP). The MSP and LSP Registers
may also be made transparent for asynchronous output
through the use of the Feed through Control (FT). There are
two output configurations which may be selected when using
the HMU16/HMU17 multipliers. The first configuration allows
the simultaneous access of the most and least significant
halves of the product. When the MSPSEL input is LOW, the
Most Significant Product will be available at the dedicated
output port (P16-31/P0-15). The Least Significant Product is
simultaneously available at the bidirectional port shared with
the Y-inputs (Y0-15/P0-15) through the use of the LSP
output enable (OEL). The other output configuration involves
multiplexing the MSP and LSP Registers onto the dedicated
output port through the use of the MSPSEL control. When
the MSPSEL control is LOW, the Most Significant Product
will be available at the dedicated output port; and when
MSPSEL is HIGH, the Least Significant Product will be
available at this port. This configuration allows access of the
entire 32-bit product by a 16-bit wide system bus.
5