ISL3873A Datasheet, PDF (4/42 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor

ISL3873A
PIN NAME
PJ4
PJ5
PJ6
PJ7
PK0
PK1
PK2
PK3
PK4
PK7
PL3
PL7
MAC Radio Interface and General Purpose Port Pins
PIN I/O TYPE
DESCRIPTION OF FUNCTION
(IF OTHER THAN I/O PORT)
CMOS BiDir, 2mA
PE1
CMOS BiDir, 2mA, 50K Pull Up
LE_IF
CMOS BiDir, 2mA
LED1
CMOS BiDir, 2mA, 50K Pull Up
RADIO_PE
CMOS BiDir, 2mA, ST, 50K Pull Down
LE_RF
CMOS BiDir, 2mA, 50K Pull Down
SYNTHCLK
CMOS BiDir, 2mA, 50K Pull Down
SYNTHDATA
CMOS BiDir, 2mA
PA_PE
CMOS BiDir, 2mA
PE2
CMOS BiDir, 2mA
CAL_EN
CMOS BiDir, 2mA
TR_SW_BAR
CMOS BiDir, 2mA, Pull Down
TR_SW
PIN NAME
PJ0
PJ1
PJ2
TCLKIN (CS_)
PIN NAME
CLKIN
XTALIN
XTALOUT
CLKOUT
BBP_CLK
PIN NAME
RX_IF_AGC
RX_RF_AGC
RX_IF_DET
RXI, ±
RXQ, ±
PIN NAME
TX_AGC_IN
TX_IF_AGC
TXI ±
TXQ ±
PIN I/O TYPE
CMOS BiDir
CMOS BiDir, 50K Pull Down
CMOS BiDir, 50K Pull Down
CMOS BiDir
PIN I/O TYPE
CMOS Input, 50K Pull Down
Analog Input
CMOS Output, 2mA
CMOS, TS Output, 2mA
Input
SERIAL EEPROM PORT PINS
DESCRIPTION
SCLK, Serial Clock
SD, Serial Data Out
MISO, Serial Data IN
CS_, Chip Select
Clocks Port Pins
DESCRIPTION
External Clock Input to MCLK prescaler (at >= 2X Desired MCLK
Frequency, Typically 44-48MHz)
32.768kHz Crystal Input
32.768kHz Crystal Output
Internal Clock Output (Selectable as MCLK, TCLK, or TOUT0)
Baseband Processor Clock. The nominal frequency for this clock is
44MHz. This is used internally to generate divide by 2 and 4 for the
transceiver clock
PIN I/O TYPE
O
O
I
I
I
Baseband Processor Receiver Port Pins
DESCRIPTION
Analog drive to the IF AGC control
Drive to the RF AGC stage attenuator. CMOS digital
Analog input to the receive power A/D converter for AGC control
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11-
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-
PIN I/O TYPE
I
O
O
O
Baseband Processor Transmitter Port Pins
DESCRIPTION
Input to the transmit power A/D converter for transmit AGC control
Analog drive to the transmit IF power control
TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/24-
TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential
29+/30-
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