ISL3873A Datasheet, PDF (14/42 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor

ISL3873A
Read to Attribute Space and Memory Mapped Registers
• WAIT will assert until the memory arbitration and access
have completed.
Buffer Access Paths, BAP0 and BAP1
• An internal Pre-Read cycle to memory is initiated by a host
Buffer Read cycle, after the internal address pointer has
auto-incremented. If the next host cycle is a read to the
same buffer, the data will be available without a memory
arbitration delay.
• A single register holds the pre-read data. Thus, any read
access to any other memory-mapped register (or the other
buffer access path) will result in the pre-read data
becoming invalidated.
• If another read cycle has invalidated the pre-read, then a
memory arbitration delay will occur on the next buffer
access path read cycle.
HIREQ-
Immediately after reset, the HIREQ- signal serves as the
RDY/BSY (per the PC Card standard). Once the ISL3873A
firmware initialization procedure is complete, HIREQ- is
configured to operate as the interrupt to the PC Card socket
controller. Both Level Mode and Pulse Mode interrupts are
supported. By default, Level mode interrupts are used, so
the interrupt source must be specifically acknowledged or
disabled before the interrupt will be removed.
RESET
When reset is de-asserted, the CIS table is initialized and,
once complete, HIREQ- is set high (HIREQ- acts as
RDY/BSY from reset and is set high to indicate the card is
ready for use). The CIS table resides in Flash memory and is
copied to RAM during firmware initialization. The host
system can then initialize the card by reading the CIS
information and writing to the configuration register.
ISA PNP
The ISL3873A can be connected to the ISA bus and operate
in a Plug and Play environment with an additional chip such
as the Fujitsu MB86703, Texas Instruments TL16PNP200A,
or Fairchild Semiconductor NM95MS15. See the Application
Note AN9874, “ISA Plug and Play with the HFA3841” for
more details.
Register Interface
The logical view of the ISL3873A from the host is a block of
32 word wide registers. These appear in IO space starting at
the base address determined by the socket controller. There
are three types of registers.
Hardware Registers (HW)
• 1 to 1 correspondence between addresses and registers.
• No memory arbitration delay, data transfer directly to/from
registers.
• AUX base and offset are write-only, to set up access
through AUX data port.
Note: All register cycles, including hardware registers, incur
a short wait state on the PC Card bus to insure the host
cycle is synchronized with the ISL3873A's internal MCLK.
Memory Mapped Registers in Data RAM (MM)
• 1 to 1 correspondence.
• Requires memory arbitration, since registers are actually
locations in ISL3873A memory.
• Attribute memory access is mapped into RAM as Base-
address + 0x400.
• AUX port provides host access to any location in
ISL3873A RAM (reserved).
Buffer Access Path (BAP)
• No 1 to 1 correspondence between register address and
memory address (due to indirect access through buffer
address pointer registers).
• Auto increment of pointer registers after each access.
• Require memory arbitration since buffers are located in
ISL3873A memory.
• Buffer access may incur additional delay for Hardware
Buffer Chaining.
Buffer Access Paths
The ISL3873A has two independent buffer access paths, which
permits concurrent read and write transfers. The firmware
provides dynamic memory allocation between Transmit and
Receive, allowing efficient memory utilization. On-the-fly
allocation of (128-byte) memory blocks as needed for reception
wastes minimal space when receiving fragments. The
ISL3873A hides management of free memory from the driver,
and allows fast response and minimum data copying for low
latency. The firmware provides direct access to TX and RX
buffers based on Frame ID (FID). This facilitates Power
Management queuing, and allows dynamic fragmentation and
de-fragmentation by the controller. Simple Allocate/De-allocate
commands ensure low host CPU overhead for memory
management.
Hardware buffer chaining provides high performance while
reading and writing buffers. Data is transferred between the
host driver and the ISL3873A by writing or reading a single
register location (the Buffer Access Path, or BAP). Each
access increments the address in the buffer memory.
Internally, the firmware allocates blocks of memory as needed
to provide the requested buffer size. These blocks may not be
contiguous, but the firmware builds a linked list of pointers
between them. When the host driver is transferring data
through a buffer access path and reaches the end of a
physical memory block, hardware in the host interface follows
the linked list so that the buffer access path points to the
beginning of the next memory block. This process is
completely transparent to the host driver, which simply writes
or reads all buffer data to the same register. If the host driver
attempts to access beyond the end of the allocated buffer,
subsequent writes are ignored, and reads will be undefined.
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