ISL3873A Datasheet, PDF (34/42 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor

Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bits 6:4
ISL3873A
CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 (Continued)
Q DAC clock.
0 = enable.
1 = disable.
RF A/D clock.
0 = enable.
1 = disable.
I A/D clock.
0 = enable.
1 = disable.
Q A/D clock.
0 = enable.
1 = disable.
CONFIGURATION REGISTER 13 ADDRESS (1Ah) R/W A/D TEST MODES 2
Standby.
1 = enable.
0 = disable.
SLEEPTX.
1 = enable.
0 = disable.
SLEEP RX.
1 = enable.
0 = disable.
SLEEP IQ.
1 = enable.
0 = disable.
Analog TX Shut_down.
1 = enable.
0 = disable.
Analog RX Shut_down.
1 = enable.
0 = disable.
Analog Standby.
1 = enable.
0 = disable.
Enable manual control of mixed signal power down signals using bits 1:7.
1 = enable.
0 = disable, normal operation (devices controlled by RESET, TX_PE, RX_PE).
CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3
Digital format, select output of I/Q and RF A/D converters.
0 = 2’s complement (normal).
1 = binary.
I/Q DAC input control. This DAC gives an analog look at various internal digital signals that are suitable for analog
representation.
000 = normal (TX filter).
001 = down converter output.
010 = E/L integrator - upper 6 bits of the TCHIPacc on (Q) and zeros on (I).
011 = I/ Q A/D’s.
100 = Bigger picker output. Upper 6 bits of FWT_I winner and FWT_Q winner.
101 = CMF weights - upper 6 bits of all 16 CMF weights are circularly shifted with full scale negative sync pulse interleaved
between them.
110 = Test Bus pins (5:0) when configured as inputs, CR32(4), ((5:0) to both I and Q inputs).
111 = Barker Correlator/ low rate samples - as selected by bit 7 CR32.
34