ISL6277HRZ Datasheet, PDF (35/37 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Mobile CPUs Using SVI 2.0

ISL6277 PIN
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ISL6277
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6277 CONTROLLER (Continued)
SYMBOL
LAYOUT GUIDELINES
LGATE1
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
PWM_Y
No special considerations.
VDD
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin with the filter resistor nearby the IC.
VDDP
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin.
LGATE2
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
PHASE2
UGATE2
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR
Channel 2 high-side MOSFET source pin instead of a general connection to PHASE2 copper is recommended for
better performance.
BOOT2
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
VIN
Place the decoupling capacitor in close proximity to the pin with a short connection to the internal GND plane.
BOOTX
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
UGATEX
PHASEX
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASEX to the high-side
MOSFET source pin instead of a general connection to the PHASEX copper is recommended for better
performance.
LGATEX
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
PWM2_NB
No special considerations.
FCCM_NB
PGOOD_NB
No special consideration.
COMP_NB
Place the compensation components in general proximity of the controller.
FB_NB
VSEN_NB
Place the filter on this pin in close proximity to the controller for good coupling.
ISUMN_NB
ISUMP_NB
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two
signals traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the
traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the
pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor.
The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
48
ISEN1_NB
35
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
FN8270.1
March 8, 2012