ISL6277HRZ Datasheet, PDF (34/37 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Mobile CPUs Using SVI 2.0

ISL6277 PIN
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14
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ISL6277
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6277 CONTROLLER (Continued)
SYMBOL
LAYOUT GUIDELINES
ISEN3
ISEN2
ISEN1
Each ISEN pin has a capacitor (C_isen) decoupling it to VSUMN and then through another capacitor (C_vsumn) to
GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small:
1. Any ISEN pin to another ISEN pin
2. Any ISEN pin to GND
The red traces in the following drawing show the loops to be minimized.
ISEN3
Phase1
Risen
L3
Ro
Cisen
Phase2
L2
Vo
Risen
Ro
ISEN2
ISEN1
GND
Cisen
Phase3
Risen
Vsumn
Cisen _Cvsumn
L1
Ro
16
ISUMP
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
17
ISUMN
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two
signals traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the
traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the
pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor.
The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
18
VSEN
Place the filter on these pins in close proximity to the controller for good coupling.
19
RTN
20
FB2
Place the compensation components in general proximity of the controller.
21
FB
22
COMP
23
PGOOD
No special consideration.
24
BOOT1
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
25
UGATE1
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR
26
PHASE1
Channel 1 high-side MOSFET source pin instead of a general connection to PHASE1 copper is recommended for
better performance.
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FN8270.1
March 8, 2012