ISL6277HRZ Datasheet, PDF (15/37 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Mobile CPUs Using SVI 2.0

ISL6277
VCRM
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
PWM2
CLOCK3
PWM3
VW
COMP
VW
VCRS1
VCRS3
VCRS2
FIGURE 9. R³â„¢ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
Diode Emulation and Period Stretching
The ISL6277 can operate in diode emulation (DE) mode to
improve light-load efficiency. In DE mode, the low-side MOSFET
conducts when the current is flowing from source to drain and
does not allow reverse current, thus emulating a diode. As
Figure 10 shows, when LGATE is on, the low-side MOSFET carries
current, creating negative voltage on the phase node due to the
voltage drop across the on-resistance. The ISL6277 monitors the
current by monitoring the phase node voltage. It turns off LGATE
when the phase node voltage reaches zero to prevent the inductor
current from reversing the direction and creating unnecessary
power loss.
PHASE
UGATE
LGATE
IL
FIGURE 10. DIODE EMULATION
If the load current is light enough, as Figure 10 shows, the
inductor current reaches and stays at zero before the next phase
node pulse, and the regulator is in discontinuous conduction
mode (DCM). If the load current is heavy enough, the inductor
current will never reach 0A, and the regulator is in CCM, although
the controller is in DE mode.
Figure 11 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size and therefore is the same, making the inductor
current triangle the same in the three cases. The ISL6277 clamps
the ripple capacitor voltage V_CRS in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit V_CRS,
naturally stretching the switching period. The inductor current
triangles move farther apart, such that the inductor current
average value is equal to the load current. The reduced switching
frequency helps increase light-load efficiency.
V_CRS
CCM/DCM
VW ^BOUNDARY
IL
V_CRS
VW ^{LIGHT DCM}
IL
V_CRS
DEEP DCM
VW
IL
FIGURE 11. PERIOD STRETCHING
Channel Configuration
Individual PWM channels of either VR can be disabled by
connecting the ISENx pin of the channel not required to +5V. For
example, placing the controller in a 2+1 configuration, as shown
in Figure 5, requires ISEN3 of the Core VR and ISEN2 of the
Northbridge VR to be tied to +5V. This disables Channel 3 of the
Core VR and Channel 2 of the Northbridge VR. ISEN1_NB must
be tied through a 10kΩ resistor to GND to prevent this pin from
pulling high and disabling the channel. Connecting ISEN1 or
ISEN1_NB to +5V will disable the corresponding VR output. This
feature allows debug of individual VR outputs.
Power-On Reset
Before the controller has sufficient bias to guarantee proper
operation, the ISL6277 requires a +5V input supply tied to VDD
and VDDP to exceed the VDD rising power-on reset (POR)
threshold. Once this threshold is reached or exceeded, the
ISL6277 has enough bias to check the state of the SVI inputs
once ENABLE is taken high. Hysteresis between the rising and
the falling thresholds assure the ISL6277 does not inadvertently
turn off unless the bias voltage drops substantially (see
“Electrical Specifications” on page 11). Note that VIN must be
present for the controller to drive the output voltage.
15
FN8270.1
March 8, 2012