ISL6277HRZ Datasheet, PDF (12/37 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Mobile CPUs Using SVI 2.0

ISL6277
Electrical Specifications Operating Conditions: V_DD = 5V, T_A = -10°C to +100°C (HRZ), T_A = -40°C to +85°C (IRZ), f_SW = 300kHz, unless
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
ISEN
Input Bias Current
20
nA
POWER-GOOD ( PGOOD & PGOOD_NB) AND PROTECTION MONITORS
PGOOD Low Voltage
PGOOD Leakage Current
PWROK High Threshold
V_OL
I_PGOOD = 4mA
I_OH
PGOOD = 3.3V
0.4
V
-1
1
µA
750
mV
VR_HOT_L Pull-down
11
Ω
PWROK Leakage Current
1
µA
VR_HOT_L Leakage Current
1
µA
GATE DRIVER
UGATE Pull-Up Resistance
UGATE Source Current
UGATE Sink Resistance
UGATE Sink Current
LGATE Pull-Up Resistance
LGATE Source Current
LGATE Sink Resistance
LGATE Sink Current
UGATE to LGATE Deadtime
LGATE to UGATE Deadtime
PROTECTION
R_UGPU
I_UGSRC
R_UGPD
I_UGSNK
R_LGPU
I_LGSRC
R_LGPD
I_LGSNK
t_UGFLGR
t_LGFUGR
200mA Source Current
UGATE - PHASE = 2.5V
250mA Sink Current
UGATE - PHASE = 2.5V
250mA Source Current
LGATE - VSSP = 2.5V
250mA Sink Current
LGATE - VSSP = 2.5V
UGATE falling to LGATE rising, no load
LGATE falling to UGATE rising, no load
1.0
1.5
Ω
2.0
A
1.0
1.5
Ω
2.0
A
1.0
1.5
Ω
2.0
A
0.5
0.9
Ω
4.0
A
23
ns
28
ns
Overvoltage Threshold
Undervoltage Threshold
Current Imbalance Threshold
OV_H
VSEN rising above setpoint for >1µs
275
325
375
mV
OV_H
VSEN falls below setpoint for >1µs
275
325
375
mV
One ISEN above another ISEN for >1.2ms
9
mV
Way Overcurrent Trip Threshold
IMONx_WOC All states, I_DROOP = 60µA, R_IMON = 135kΩ
15
µA
[IMONx Current Based Detection]
Overcurrent Trip Threshold
[IMONx Voltage Based Detection]
LOGIC THRESHOLDS
V_{IMONx_OCP}
All states, I_DROOP = 45µA,
I_IMONx = 11.25µA , R_IMON = 135kΩ
1.485 1.51 1.535
V
ENABLE Input Low
ENABLE Input High
ENABLE Leakage Current
V_IL
V_IH
V_IH
I_ENABLE
HRZ
IRZ
ENABLE = 0V
ENABLE = 1V
1
V
1.6
V
1.65
V
-1
0
1
µA
18
35
µA
SVT Impedance
50
Ω
SVC, SVD Input Low
SVC, SVD Input High
SVC, SVD Leakage
V_IL
% of VDDIO
V_IH
% of VDDIO
70
ENABLE = 0V, SVC, SVD = 0V and 1V
-1
30
%
%
1
µA
ENABLE = 1V, SVC, SVD = 1V
-5
1
µA
ENABLE = 1V, SVC, SVD = 0V
-35
-20
-5
µA
PWM
PWM Output Low
PWM Output High
PWM Tri-State Leakage
V_0L
Sinking 5mA
V_0H
Sourcing 5mA
PWM = 2.5V
1.0
V
3.5
V
0.5
µA
12
FN8270.1
March 8, 2012